From patchwork Wed Oct 19 09:59:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 9384599 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AC1DE60762 for ; Wed, 19 Oct 2016 15:47:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9CB202960B for ; Wed, 19 Oct 2016 15:47:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 914EB2960E; Wed, 19 Oct 2016 15:47:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2EA70295D9 for ; Wed, 19 Oct 2016 15:47:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S945530AbcJSPqx (ORCPT ); Wed, 19 Oct 2016 11:46:53 -0400 Received: from mail-lf0-f41.google.com ([209.85.215.41]:33352 "EHLO mail-lf0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S943472AbcJSPqu (ORCPT ); Wed, 19 Oct 2016 11:46:50 -0400 Received: by mail-lf0-f41.google.com with SMTP id x79so32283968lff.0 for ; Wed, 19 Oct 2016 08:46:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UfvTc4kW1wY9/O9DDtWZ//RLrTotLhM5AnCqiGT9Zoc=; b=bvfgFuU2AFYoaSI5ZgdotXTpTzql/ih9lfTipyjnNML+HASoz06V3k7c71gum3DSl1 hBHmfvmKy1xAQSawGjmslq09q83vdFs2HHJfBP7zHPYV+Q8YzmrLfsmdhOEfVgUSPV/3 BAexd8ZJbONu8Q7+f+7p2i6iFC+dJtRVJTnwg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UfvTc4kW1wY9/O9DDtWZ//RLrTotLhM5AnCqiGT9Zoc=; b=kSl9498LfcS8ABn7xLkKBirXDQiGFAmLJ6GFjmLuVaEJesBSRPgYz+ZK65M6w2EqzA tFRsV35uMI2Au6GFkb8f0VsizbeIMjyy7YIxjVboJD3dToMviv3NpW6QUXDabk5LFSbG 7pHwhnUeAGFB/79Maqyed03E2azLNiGvOv5opYi/dP4tQyuhfpUW40Wo/Y8jcJAambix o+Ci59tTViz+lK6/8pUQN2bCa47pSP+GvgyfkF8Eb5lAJi6B2RKAdAhIqlz4cDSIKs7J IhmMBr8+SEpBfwQnlQRqZ5BVZafAUq6nZmrvOXcS2rM3BBCF3j2uShUOSYdfJbA5cP4Z O+jg== X-Gm-Message-State: AA6/9RkAQHksixPFGTqQGkZ0ojqpgcITOTPHACisnaYuhCyPat6nzuBZmgjGebDDvOOGAiuw X-Received: by 10.25.99.85 with SMTP id x82mr4076688lfb.105.1476871166232; Wed, 19 Oct 2016 02:59:26 -0700 (PDT) Received: from linuslaptop.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id h88sm10301633lfi.6.2016.10.19.02.59.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Oct 2016 02:59:25 -0700 (PDT) From: Linus Walleij To: "Rafael J . Wysocki" , Viresh Kumar Cc: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Russell King , Linus Walleij , "Rafael J . Wysocki" Subject: [PATCH 2/5] ARM: dts: Add Integrator/AP cpus node and operating points Date: Wed, 19 Oct 2016 11:59:11 +0200 Message-Id: <1476871154-32243-3-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1476871154-32243-1-git-send-email-linus.walleij@linaro.org> References: <1476871154-32243-1-git-send-email-linus.walleij@linaro.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the cpus node to the Integrator/AP device tree so that we have a proper placeholder to put in the DT-defined operating points for the generic DT/OPP cpufreq driver, along with the proper operating points. The old Integrator cpufreq driver would resolve the max frequency to 71MHz, and the min frequency to 12 MHz, but the clock driver can actually handle any frequency inbetween so I picked a few select frequencies as OPPs. The cpufreq framework doesn't seem to deal with sliding frequency scales, only fixed points so 7 OPPs is better than 2 atleast. We define a CPU node since this is required for cpufreq-dt, however we do not define any compatible string for the CPU since this architecture has pluggable CPU modules and we do not know which one will be used. If necessary, the CPU compatible can be filled in by the boot loader, but for just cpufreq-dt it is not required. Cc: Rafael J. Wysocki Cc: Viresh Kumar Cc: Russell King Signed-off-by: Linus Walleij --- arch/arm/boot/dts/integratorap.dts | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index 6f16d09dc5a4..e8b249f92fb3 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -10,6 +10,41 @@ compatible = "arm,integrator-ap"; dma-ranges = <0x80000000 0x0 0x80000000>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + /* + * Since the board has pluggable CPU modules, we + * cannot define a proper compatible here. Let the + * boot loader fill in the apropriate compatible + * string if necessary. + */ + /* compatible = "arm,arm926ej-s"; */ + reg = <0>; + /* + * The documentation in ARM DUI 0138E page 3-12 states + * that the maximum frequency for this clock is 200 MHz + * but painful trial-and-error has proved to me that it + * is actually just hanging the system above 71 MHz. + * Sad but true. + */ + /* kHz uV */ + operating-points = <71000 0 + 66000 0 + 60000 0 + 48000 0 + 36000 0 + 24000 0 + 12000 0>; + clocks = <&cmosc>; + clock-names = "cpu"; + clock-latency = <1000000>; /* 1 ms */ + }; + }; + aliases { arm,timer-primary = &timer2; arm,timer-secondary = &timer1;