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Mon, 16 Jan 2017 06:45:31 +0000 (GMT) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20170116064528eucas1p207c927835e33568e447c5a42ad18d0a7~aLZEe4A1_1219312193eucas1p2d; Mon, 16 Jan 2017 06:45:28 +0000 (GMT) X-AuditID: cbfec7ef-f79d26d00000420c-b4-587c6c0b3382 Received: from eusync2.samsung.com ( [203.254.199.212]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id B3.B9.10233.20C6C785; Mon, 16 Jan 2017 06:45:22 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OJV00BS81FJUN70@eusync2.samsung.com>; Mon, 16 Jan 2017 06:45:28 +0000 (GMT) From: Marek Szyprowski To: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , Bartlomiej Zolnierkiewicz Subject: [PATCH 10/12] pinctrl: samsung: Move retention control from mach-exynos to the pinctrl driver Date: Mon, 16 Jan 2017 07:45:05 +0100 Message-id: <1484549107-5957-11-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1484549107-5957-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJIsWRmVeSWpSXmKPExsWy7djPc7rcOTURBgtmqFpsnLGe1eL8+Q3s FlP+LGey2PT4GqvF5vl/GC0+9x5htJhxfh+Txdojd9ktDr9pZ7VYtesPowOXx85Zd9k9Nq3q ZPO4c20Pm8fmJfUefVtWMXp83iQXwBbFZZOSmpNZllqkb5fAlfHszEXGgofVFU3H57I3MO7O 6GLk5JAQMJF4umkJM4QtJnHh3no2EFtIYBmjRO9umS5GLiD7M6PE1NutTF2MHGAN0/4FQcSB ak5+v8EI4TQwSTxuO88C0s0mYCjR9baLDSQhItDMKDHz7l52EIdZoI9J4vPmvYwgVcICGRIb DrwBs1kEVCUebX4HtoJXwEPi0HtJiJPkJE4em8wKYnMChSfua2UBmSMhMJld4taMRywQJ8lK bDoA9YKLxIcZc9khbGGJV8e3QNkyEpcnd7NA2P2MEk2t2hD2DEaJc295IWxricPHL4LtYhbg k5i0bTozxHheiY42IQjTQ2LttmgI01Hi23cPiNdnM0r86TjKOIFRZgEjwypGkdTS4tz01GJD veLE3OLSvHS95PzcTYzACD/97/j7HYxPm0MOMQpwMCrx8C7YUR0hxJpYVlyZe4hRgoNZSYTX LbMmQog3JbGyKrUoP76oNCe1+BCjNAeLkjjv3gVXwoUE0hNLUrNTUwtSi2CyTBycUg2MXHUh ERNS1mYsn392aS0XF++HGY9Xmj6T+Vqj3/bgz4St/xbmhZwuSfkXHXJrXcrvewkdq19VlPD6 fSvK039iHvphp1I9/2WLg2EOXfxmC/2W7XI9dfHkqq/nNttW1TT8LFo50y4ufDbnkXUasi7v /k1SiOmtY2K8zDuxL9cwQPkqw9rpX3l5lFiKMxINtZiLihMBrkf3EewCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrDLMWRmVeSWpSXmKPExsVy+t/xK7pMOTURBptvy1tsnLGe1eL8+Q3s FlP+LGey2PT4GqvF5vl/GC0+9x5htJhxfh+Txdojd9ktDr9pZ7VYtesPowOXx85Zd9k9Nq3q ZPO4c20Pm8fmJfUefVtWMXp83iQXwBblZpORmpiSWqSQmpecn5KZl26rFBripmuhpJCXmJtq qxSh6xsSpKRQlphTCuQZGaABB+cA92AlfbsEt4xnZy4yFjysrmg6Ppe9gXF3RhcjB4eEgInE tH9BXYycQKaYxIV769m6GLk4hASWMEr8njCHGcJpYpLoWj+VHaSKTcBQouttF1iViEAzo0TD kl4wh1lgApPEzE8NTCBVwgIZEhsOvGEEsVkEVCUebX7HBLKOV8BD4tB7SYh1chInj01mBbE5 gcIT97WygNhCAu4SM15NZZ7AyLuAkWEVo0hqaXFuem6xkV5xYm5xaV66XnJ+7iZGYMhvO/Zz yw7GrnfBhxgFOBiVeHgX7KiOEGJNLCuuzD3EKMHBrCTC65ZZEyHEm5JYWZValB9fVJqTWnyI 0RToponMUqLJ+cB4zCuJNzQxNLc0NDK2sDA3MlIS55364Uq4kEB6YklqdmpqQWoRTB8TB6dU A6PrAwPNeWmHXHhFskLlHSUWXJj2N+TQFrEZFS+/bU6rF5mZvutsYvJytW2ftgUu5D5uOzH0 +Y3ajT1dVg27t3XIv1Q63vjsh1+Q/YZ5FxbPV98a/+mYQuiOmWrh+cXXZH8WqTBYyOecs1oW H35qfli2E7+ajc+a4rqIv+azxPlKF/k8mPFyyWUlluKMREMt5qLiRACQJI16jwIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170116064528eucas1p207c927835e33568e447c5a42ad18d0a7 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRs=?= =?UTF-8?B?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?TWFyZWsgU3p5cHJvd3NraRtTUlBPTC1LZXJuZWwgKFRQKRtT?= =?UTF-8?B?YW1zdW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170116064528eucas1p207c927835e33568e447c5a42ad18d0a7 X-RootMTR: 20170116064528eucas1p207c927835e33568e447c5a42ad18d0a7 References: <1484549107-5957-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch moves pad retention control from PMU driver to Exynos pin controller driver. This helps to avoid possible ordering and logical dependencies between machine, PMU and pin control code. Till now it worked fine only because sys_ops for PMU and pin controller were called in registration order. This is also a preparation for adding new features to Exynos pin controller driver, like runtime power management and suspending individual pin controllers, which might be a part of some power domain. Signed-off-by: Marek Szyprowski --- arch/arm/mach-exynos/suspend.c | 64 ------------- drivers/pinctrl/samsung/pinctrl-exynos.c | 149 +++++++++++++++++++++++++++++++ 2 files changed, 149 insertions(+), 64 deletions(-) diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 25e7c5326259..312d3a886e92 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -57,7 +57,6 @@ struct exynos_wkup_irq { struct exynos_pm_data { const struct exynos_wkup_irq *wkup_irq; unsigned int wake_disable_mask; - const unsigned int *release_ret_regs; void (*pm_prepare)(void); void (*pm_resume_prepare)(void); @@ -95,47 +94,6 @@ struct exynos_pm_data { { /* sentinel */ }, }; -static const unsigned int exynos_release_ret_regs[] = { - S5P_PAD_RET_MAUDIO_OPTION, - S5P_PAD_RET_GPIO_OPTION, - S5P_PAD_RET_UART_OPTION, - S5P_PAD_RET_MMCA_OPTION, - S5P_PAD_RET_MMCB_OPTION, - S5P_PAD_RET_EBIA_OPTION, - S5P_PAD_RET_EBIB_OPTION, - REG_TABLE_END, -}; - -static const unsigned int exynos3250_release_ret_regs[] = { - S5P_PAD_RET_MAUDIO_OPTION, - S5P_PAD_RET_GPIO_OPTION, - S5P_PAD_RET_UART_OPTION, - S5P_PAD_RET_MMCA_OPTION, - S5P_PAD_RET_MMCB_OPTION, - S5P_PAD_RET_EBIA_OPTION, - S5P_PAD_RET_EBIB_OPTION, - S5P_PAD_RET_MMC2_OPTION, - S5P_PAD_RET_SPI_OPTION, - REG_TABLE_END, -}; - -static const unsigned int exynos5420_release_ret_regs[] = { - EXYNOS_PAD_RET_DRAM_OPTION, - EXYNOS_PAD_RET_MAUDIO_OPTION, - EXYNOS_PAD_RET_JTAG_OPTION, - EXYNOS5420_PAD_RET_GPIO_OPTION, - EXYNOS5420_PAD_RET_UART_OPTION, - EXYNOS5420_PAD_RET_MMCA_OPTION, - EXYNOS5420_PAD_RET_MMCB_OPTION, - EXYNOS5420_PAD_RET_MMCC_OPTION, - EXYNOS5420_PAD_RET_HSI_OPTION, - EXYNOS_PAD_RET_EBIA_OPTION, - EXYNOS_PAD_RET_EBIB_OPTION, - EXYNOS5420_PAD_RET_SPI_OPTION, - EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, - REG_TABLE_END, -}; - static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) { const struct exynos_wkup_irq *wkup_irq; @@ -441,15 +399,6 @@ static int exynos5420_pm_suspend(void) return 0; } -static void exynos_pm_release_retention(void) -{ - unsigned int i; - - for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++) - pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR, - pm_data->release_ret_regs[i]); -} - static void exynos_pm_resume(void) { u32 cpuid = read_cpuid_part(); @@ -457,9 +406,6 @@ static void exynos_pm_resume(void) if (exynos_pm_central_resume()) goto early_wakeup; - /* For release retention */ - exynos_pm_release_retention(); - if (cpuid == ARM_CPU_PART_CORTEX_A9) scu_enable(S5P_VA_SCU); @@ -481,9 +427,6 @@ static void exynos3250_pm_resume(void) if (exynos_pm_central_resume()) goto early_wakeup; - /* For release retention */ - exynos_pm_release_retention(); - pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); if (call_firmware_op(resume) == -ENOSYS @@ -521,9 +464,6 @@ static void exynos5420_pm_resume(void) if (exynos_pm_central_resume()) goto early_wakeup; - /* For release retention */ - exynos_pm_release_retention(); - pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3); early_wakeup: @@ -636,7 +576,6 @@ static void exynos_suspend_finish(void) static const struct exynos_pm_data exynos3250_pm_data = { .wkup_irq = exynos3250_wkup_irq, .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos3250_release_ret_regs, .pm_suspend = exynos_pm_suspend, .pm_resume = exynos3250_pm_resume, .pm_prepare = exynos3250_pm_prepare, @@ -646,7 +585,6 @@ static void exynos_suspend_finish(void) static const struct exynos_pm_data exynos4_pm_data = { .wkup_irq = exynos4_wkup_irq, .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos_release_ret_regs, .pm_suspend = exynos_pm_suspend, .pm_resume = exynos_pm_resume, .pm_prepare = exynos_pm_prepare, @@ -656,7 +594,6 @@ static void exynos_suspend_finish(void) static const struct exynos_pm_data exynos5250_pm_data = { .wkup_irq = exynos5250_wkup_irq, .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)), - .release_ret_regs = exynos_release_ret_regs, .pm_suspend = exynos_pm_suspend, .pm_resume = exynos_pm_resume, .pm_prepare = exynos_pm_prepare, @@ -666,7 +603,6 @@ static void exynos_suspend_finish(void) static const struct exynos_pm_data exynos5420_pm_data = { .wkup_irq = exynos5250_wkup_irq, .wake_disable_mask = (0x7F << 7) | (0x1F << 1), - .release_ret_regs = exynos5420_release_ret_regs, .pm_resume_prepare = exynos5420_prepare_pm_resume, .pm_resume = exynos5420_pm_resume, .pm_suspend = exynos5420_pm_suspend, diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 70b94ad10cc1..652d3eabe1e5 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -28,7 +28,10 @@ #include #include #include +#include #include +#include +#include #include "pinctrl-samsung.h" #include "pinctrl-exynos.h" @@ -690,6 +693,58 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) }, }; +/* Pad retention control code for accessing PMU regmap */ +static atomic_t exynos_shared_retention_refcnt; + +static void exynos_retention_on(struct samsung_pinctrl_drv_data *drvdata) +{ + if (drvdata->retention_ctrl->refcnt) + atomic_inc(drvdata->retention_ctrl->refcnt); +} + +static void exynos_retention_off(struct samsung_pinctrl_drv_data *drvdata) +{ + struct regmap *pmu_regs = drvdata->retention_ctrl->priv; + int i; + + if (drvdata->retention_ctrl->refcnt && + !atomic_dec_and_test(drvdata->retention_ctrl->refcnt)) + return; + + for (i = 0; i < drvdata->retention_ctrl->nr_regs; i++) + regmap_write(pmu_regs, drvdata->retention_ctrl->regs[i], + drvdata->retention_ctrl->value); +} + +static struct samsung_retention_ctrl * +exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data) +{ + struct samsung_retention_ctrl *ctrl; + struct regmap *pmu_regs; + + ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return NULL; + + pmu_regs = exynos_get_pmu_regs(); + if (!pmu_regs) { + dev_err(drvdata->dev, + "failed to lookup PMU regmap, no support for pad retention\n"); + return NULL; + } + + ctrl->priv = pmu_regs; + ctrl->regs = data->regs; + ctrl->nr_regs = data->nr_regs; + ctrl->value = data->value; + ctrl->refcnt = data->refcnt; + ctrl->on = exynos_retention_on; + ctrl->off = exynos_retention_off; + + return ctrl; +} + /* pin banks of exynos3250 pin-controller 0 */ static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), @@ -722,6 +777,30 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) }; /* + * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle + * them all together + */ +static const u32 exynos3250_retention_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, + S5P_PAD_RET_MMC2_OPTION, + S5P_PAD_RET_SPI_OPTION, +}; + +static const struct samsung_retention_data exynos3250_retention_data __initconst = { + .regs = exynos3250_retention_regs, + .nr_regs = ARRAY_SIZE(exynos3250_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes * two gpio/pin-mux/pinconfig controllers. */ @@ -733,6 +812,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos3250_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos3250_pin_banks1, @@ -741,6 +821,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos3250_retention_data, }, }; @@ -793,6 +874,36 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), }; +/* PMU pad retention groups registers for Exynos4 (without audio) */ +static const u32 exynos4_retention_regs[] = { + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, +}; + +static const struct samsung_retention_data exynos4_retention_data __initconst = { + .regs = exynos4_retention_regs, + .nr_regs = ARRAY_SIZE(exynos4_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* PMU retention control for audio pins can be tied to audio pin bank */ +static const u32 exynos4_audio_retention_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, +}; + +static const struct samsung_retention_data exynos4_audio_retention_data __initconst = { + .regs = exynos4_audio_retention_regs, + .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .init = exynos_retention_init, +}; + /* * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes * three gpio/pin-mux/pinconfig controllers. @@ -805,6 +916,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos4210_pin_banks1, @@ -813,10 +925,12 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos4210_pin_banks2, .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), + .retention_data = &exynos4_audio_retention_data, }, }; @@ -890,6 +1004,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos4x12_pin_banks1, @@ -898,6 +1013,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos4x12_pin_banks2, @@ -905,6 +1021,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, }, { /* pin-controller instance 3 data */ .pin_banks = exynos4x12_pin_banks3, @@ -984,6 +1101,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_wkup_init = exynos_eint_wkup_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos5250_pin_banks1, @@ -991,6 +1109,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos5250_pin_banks2, @@ -1005,6 +1124,7 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .eint_gpio_init = exynos_eint_gpio_init, .suspend = exynos_pinctrl_suspend, .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, }, }; @@ -1231,6 +1351,30 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), }; +/* PMU pad retention groups registers for Exynos5420 (without audio) */ +static const u32 exynos5420_retention_regs[] = { + EXYNOS_PAD_RET_DRAM_OPTION, + EXYNOS_PAD_RET_JTAG_OPTION, + EXYNOS5420_PAD_RET_GPIO_OPTION, + EXYNOS5420_PAD_RET_UART_OPTION, + EXYNOS5420_PAD_RET_MMCA_OPTION, + EXYNOS5420_PAD_RET_MMCB_OPTION, + EXYNOS5420_PAD_RET_MMCC_OPTION, + EXYNOS5420_PAD_RET_HSI_OPTION, + EXYNOS_PAD_RET_EBIA_OPTION, + EXYNOS_PAD_RET_EBIB_OPTION, + EXYNOS5420_PAD_RET_SPI_OPTION, + EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, +}; + +static const struct samsung_retention_data exynos5420_retention_data __initconst = { + .regs = exynos5420_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5420_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + /* * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes * four gpio/pin-mux/pinconfig controllers. @@ -1242,26 +1386,31 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 1 data */ .pin_banks = exynos5420_pin_banks1, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 2 data */ .pin_banks = exynos5420_pin_banks2, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 3 data */ .pin_banks = exynos5420_pin_banks3, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, }, { /* pin-controller instance 4 data */ .pin_banks = exynos5420_pin_banks4, .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos4_audio_retention_data, }, };