From patchwork Mon Mar 6 15:23:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gerlach X-Patchwork-Id: 9606985 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B49B660414 for ; Mon, 6 Mar 2017 15:26:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A42F328447 for ; Mon, 6 Mar 2017 15:26:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 98D602844E; Mon, 6 Mar 2017 15:26:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 28BF828447 for ; Mon, 6 Mar 2017 15:26:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754406AbdCFP0G (ORCPT ); Mon, 6 Mar 2017 10:26:06 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:13226 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754464AbdCFP0E (ORCPT ); Mon, 6 Mar 2017 10:26:04 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v26FO9OL025374; Mon, 6 Mar 2017 09:24:09 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1488813849; bh=OFU9AN0IgJI8PDTZg9PpoeTnc4tkehVUnWjVebnoBlQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IkAuuKVJLJ23g0Q5nNiQe5mfPup9OqXox3lx4D9rzAQbaJo1UXN3oBFiVya3avre+ 4DlfkMm4e4mormTQx6M1jg/vk3UEDR0KGfFi2B/zIhY2uhEaATkMJUAvX3wo72Q8vA HiQ6bwgmHAacpDoOb+AANti9OOZCwnGl+igsjmbg= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v26FO4Vt006132; Mon, 6 Mar 2017 09:24:04 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Mon, 6 Mar 2017 09:24:03 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v26FO3Jn019339; Mon, 6 Mar 2017 09:24:04 -0600 Received: from localhost (uda0274052.am.dhcp.ti.com [128.247.83.19]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v26FO3306459; Mon, 6 Mar 2017 09:24:03 -0600 (CST) From: Dave Gerlach To: Tony Lindgren CC: , , , Viresh Kumar , , Rob Herring , Nishanth Menon , Dave Gerlach , Lukasz Majewski , Yegor Yefremov Subject: [PATCH 4/5] ARM: dts: dra7: Add updated operating-points-v2 table for cpu Date: Mon, 6 Mar 2017 09:23:41 -0600 Message-ID: <1488813822-26042-5-git-send-email-d-gerlach@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1488813822-26042-1-git-send-email-d-gerlach@ti.com> References: <1488813822-26042-1-git-send-email-d-gerlach@ti.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP After the ti-cpufreq driver has been added, we can now drop the operating-points table present in dra7.dtsi for the cpu and add an operating-points-v2 table with all OPPs available for all silicon revisions. Also add necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime as part of the operating-points table. As we now need to define voltage ranges for each OPP, we define the minimum and maximum voltage to match the ranges possible for AVS class0 voltage as defined by the DRA7/AM57 Data Manual, with the exception of using a range for OPP_OD based on historical data to ensure that SoCs from older lots still continue to boot, even though more optimal voltages are now the standard. Once an AVS Class0 driver is in place it will be possible for these OPP voltages to be adjusted to any voltage within the provided range. Information from SPRS953, Revised December 2015. Signed-off-by: Dave Gerlach Reviewed-by: Lukasz Majewski --- arch/arm/boot/dts/dra7.dtsi | 24 +++++++++++++++++++----- arch/arm/boot/dts/dra74x.dtsi | 5 +++++ 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 2c9e56f4aac5..e9dc314b0dcf 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -81,11 +81,7 @@ compatible = "arm,cortex-a15"; reg = <0>; - operating-points = < - /* kHz uV */ - 1000000 1060000 - 1176000 1160000 - >; + operating-points-v2 = <&cpu0_opp_table>; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -99,6 +95,24 @@ }; }; + cpu0_opp_table: opp-table { + compatible = "operating-points-v2-ti-cpu"; + syscon = <&scm_wkup>; + + opp_nom@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1060000 850000 1150000>; + opp-supported-hw = <0xFF 0x01>; + opp-suspend; + }; + + opp_od@1176000000 { + opp-hz = /bits/ 64 <1176000000>; + opp-microvolt = <1160000 885000 1160000>; + opp-supported-hw = <0xFF 0x02>; + }; + }; + /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 0a78347e6615..24e6746c5b26 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -17,6 +17,7 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; + operating-points-v2 = <&cpu0_opp_table>; }; }; @@ -79,6 +80,10 @@ }; }; +&cpu0_opp_table { + opp-shared; +}; + &dss { reg = <0x58000000 0x80>, <0x58004054 0x4>,