| Message ID | 1491223345-24386-2-git-send-email-mperttunen@nvidia.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
On Mon, Apr 03, 2017 at 03:42:24PM +0300, Mikko Perttunen wrote: > The Tegra186 CCPLEX_CLUSTER area contains memory-mapped > registers that initiate CPU frequency/voltage transitions. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > --- > .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt > > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt > new file mode 100644 > index 000000000000..50cd615219e9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt > @@ -0,0 +1,22 @@ > +NVIDIA Tegra CCPLEX_CLUSTER area > + > +Required properties: > +- compatible: Should contain one of the following: > + - "nvidia,tegra186-ccplex-cluster": for Tegra186 > +- reg: Must contain an (offset, length) pair of the register set for each > + entry in reg-names. > +- reg-names: Must include the following entries: > + - "a57": Public aperture for A57 CPU cluster > + - "denver": Public aperture for Denver CPU cluster > +- nvidia,bpmp: Phandle to BPMP device that can be queried for OPP tables "phandle" > +Example: > + > + ccplex@e000000 { > + compatible = "nvidia,tegra186-ccplex-cluster"; > + reg = <0x0 0x0e060000 0x0 0x1000>, > + <0x0 0x0e070000 0x0 0x1000>; > + reg-names = "a57", "denver"; > + > + nvidia,bpmp = <&bpmp>; > + }; Where's the information about the register offsets coming from? The TRM says that CCPLEX_CLUSTER has a single aperture from 0x0e000000 to 0x0e3fffff. Thierry
On 03/04/17 13:42, Mikko Perttunen wrote: > The Tegra186 CCPLEX_CLUSTER area contains memory-mapped > registers that initiate CPU frequency/voltage transitions. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > --- > .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt > > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt > new file mode 100644 > index 000000000000..50cd615219e9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt > @@ -0,0 +1,22 @@ > +NVIDIA Tegra CCPLEX_CLUSTER area > + > +Required properties: > +- compatible: Should contain one of the following: > + - "nvidia,tegra186-ccplex-cluster": for Tegra186 Nit pick ... any reason why we append 'cluster' here? The TRM just says the "CPU Complex" consists of two CPU clusters. So "nvidia,tegra186-cpu-complex" or "nvidia,tegra186-ccplex" seems fine. BTW, I do see references in the TRM to CCPLEX_CLUSTER0/1, but never CCPLEX_CLUSTER in reference to both. I think it is just CCPLEX AFAICT. Cheers Jon
On 04/03/2017 05:06 PM, Thierry Reding wrote: > On Mon, Apr 03, 2017 at 03:42:24PM +0300, Mikko Perttunen wrote: >> The Tegra186 CCPLEX_CLUSTER area contains memory-mapped >> registers that initiate CPU frequency/voltage transitions. >> >> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> >> --- >> .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt >> >> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt >> new file mode 100644 >> index 000000000000..50cd615219e9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt >> @@ -0,0 +1,22 @@ >> +NVIDIA Tegra CCPLEX_CLUSTER area >> + >> +Required properties: >> +- compatible: Should contain one of the following: >> + - "nvidia,tegra186-ccplex-cluster": for Tegra186 >> +- reg: Must contain an (offset, length) pair of the register set for each >> + entry in reg-names. >> +- reg-names: Must include the following entries: >> + - "a57": Public aperture for A57 CPU cluster >> + - "denver": Public aperture for Denver CPU cluster >> +- nvidia,bpmp: Phandle to BPMP device that can be queried for OPP tables > > "phandle" Will fix. > >> +Example: >> + >> + ccplex@e000000 { >> + compatible = "nvidia,tegra186-ccplex-cluster"; >> + reg = <0x0 0x0e060000 0x0 0x1000>, >> + <0x0 0x0e070000 0x0 0x1000>; >> + reg-names = "a57", "denver"; >> + >> + nvidia,bpmp = <&bpmp>; >> + }; > > Where's the information about the register offsets coming from? The TRM > says that CCPLEX_CLUSTER has a single aperture from 0x0e000000 to > 0x0e3fffff. Some internal document with a name related to Denver power management, IIRC. I'll link it to you tomorrow. > > Thierry >
On 04/03/2017 05:24 PM, Jon Hunter wrote: > > On 03/04/17 13:42, Mikko Perttunen wrote: >> The Tegra186 CCPLEX_CLUSTER area contains memory-mapped >> registers that initiate CPU frequency/voltage transitions. >> >> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> >> --- >> .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22 ++++++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt >> >> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt >> new file mode 100644 >> index 000000000000..50cd615219e9 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt >> @@ -0,0 +1,22 @@ >> +NVIDIA Tegra CCPLEX_CLUSTER area >> + >> +Required properties: >> +- compatible: Should contain one of the following: >> + - "nvidia,tegra186-ccplex-cluster": for Tegra186 > > Nit pick ... any reason why we append 'cluster' here? The TRM just says > the "CPU Complex" consists of two CPU clusters. So > "nvidia,tegra186-cpu-complex" or "nvidia,tegra186-ccplex" seems fine. > > BTW, I do see references in the TRM to CCPLEX_CLUSTER0/1, but never > CCPLEX_CLUSTER in reference to both. I think it is just CCPLEX AFAICT. The reason was that the MMIO aperture is called "CCPLEX_CLUSTER" in the address map. But I agree it's not a very descriptive name. > > Cheers > Jon >
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt new file mode 100644 index 000000000000..50cd615219e9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt @@ -0,0 +1,22 @@ +NVIDIA Tegra CCPLEX_CLUSTER area + +Required properties: +- compatible: Should contain one of the following: + - "nvidia,tegra186-ccplex-cluster": for Tegra186 +- reg: Must contain an (offset, length) pair of the register set for each + entry in reg-names. +- reg-names: Must include the following entries: + - "a57": Public aperture for A57 CPU cluster + - "denver": Public aperture for Denver CPU cluster +- nvidia,bpmp: Phandle to BPMP device that can be queried for OPP tables + +Example: + + ccplex@e000000 { + compatible = "nvidia,tegra186-ccplex-cluster"; + reg = <0x0 0x0e060000 0x0 0x1000>, + <0x0 0x0e070000 0x0 0x1000>; + reg-names = "a57", "denver"; + + nvidia,bpmp = <&bpmp>; + };
The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> --- .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt