From patchwork Mon Apr 3 12:42:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 9659515 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DEF6D60364 for ; Mon, 3 Apr 2017 12:44:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D55FA28419 for ; Mon, 3 Apr 2017 12:44:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CA37E2843B; Mon, 3 Apr 2017 12:44:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5933E28422 for ; Mon, 3 Apr 2017 12:44:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752980AbdDCMot (ORCPT ); Mon, 3 Apr 2017 08:44:49 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:4422 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752945AbdDCMos (ORCPT ); Mon, 3 Apr 2017 08:44:48 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 03 Apr 2017 05:44:52 -0700 Received: from HQMAIL107.nvidia.com ([172.20.13.39]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 03 Apr 2017 05:41:23 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 03 Apr 2017 05:41:23 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Mon, 3 Apr 2017 12:44:47 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Mon, 3 Apr 2017 12:44:47 +0000 Received: from mperttunen-lnx.Nvidia.com (Not Verified[10.21.26.175]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Mon, 03 Apr 2017 05:44:46 -0700 From: Mikko Perttunen To: , , , CC: , , , Mikko Perttunen Subject: [PATCH 2/3] dt-bindings: Add bindings for nvidia, tegra186-ccplex-cluster Date: Mon, 3 Apr 2017 15:42:24 +0300 Message-ID: <1491223345-24386-2-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1491223345-24386-1-git-send-email-mperttunen@nvidia.com> References: <1491223345-24386-1-git-send-email-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Tegra186 CCPLEX_CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Mikko Perttunen --- .../arm/tegra/nvidia,tegra186-ccplex-cluster.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt new file mode 100644 index 000000000000..50cd615219e9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-ccplex-cluster.txt @@ -0,0 +1,22 @@ +NVIDIA Tegra CCPLEX_CLUSTER area + +Required properties: +- compatible: Should contain one of the following: + - "nvidia,tegra186-ccplex-cluster": for Tegra186 +- reg: Must contain an (offset, length) pair of the register set for each + entry in reg-names. +- reg-names: Must include the following entries: + - "a57": Public aperture for A57 CPU cluster + - "denver": Public aperture for Denver CPU cluster +- nvidia,bpmp: Phandle to BPMP device that can be queried for OPP tables + +Example: + + ccplex@e000000 { + compatible = "nvidia,tegra186-ccplex-cluster"; + reg = <0x0 0x0e060000 0x0 0x1000>, + <0x0 0x0e070000 0x0 0x1000>; + reg-names = "a57", "denver"; + + nvidia,bpmp = <&bpmp>; + };