From patchwork Fri Feb 9 10:57:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Gautam X-Patchwork-Id: 10208761 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8A5F9602D8 for ; Fri, 9 Feb 2018 10:57:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7588C28907 for ; Fri, 9 Feb 2018 10:57:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 67B8828A70; Fri, 9 Feb 2018 10:57:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D8BC928907 for ; Fri, 9 Feb 2018 10:57:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750895AbeBIK52 (ORCPT ); Fri, 9 Feb 2018 05:57:28 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:50774 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750828AbeBIK51 (ORCPT ); Fri, 9 Feb 2018 05:57:27 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7BFF860A54; Fri, 9 Feb 2018 10:57:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518173846; bh=Q24ZyYaHgIWp0OzxecNWHrM4tK3JKKwU3NkBVzYHT2w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XuF00p+yh/Ewih7M6L71GYDHWROfrGmz/fRg3/l7ipA4ZcZovQ5drIassqzQkcetp s5pmS/7twYEzzriGaOeSTRCWdQQUqeH1YY9p0CBKz9TmGWx1Paog7GX6lqZWNYNQs+ ZBzXDTg4zNy1Y/r6FGyWj8NdQbCeNiuhIub7I2Hw= Received: from blr-ubuntu-41.ap.qualcomm.com (blr-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.18.19]) (using TLSv1.1 with cipher ECDHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: vivek.gautam@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4EABE60314; Fri, 9 Feb 2018 10:57:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518173845; bh=Q24ZyYaHgIWp0OzxecNWHrM4tK3JKKwU3NkBVzYHT2w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mtS6cXUH602K/HMNqK6Oefk75SgPyPCFwLPII7kzqE2hGKLHNqm9VEEehPAC1vjzd Q1zOqtGaxVDxdI1C+0EDBeuLh0h2wNOU3dmBRRmBjVzypyEPPUQv8U+yGBV12aXmQ2 XQkim05rA8rEEQz6bSg9d2LdwWuQv3tOtRoVKlik= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4EABE60314 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vivek.gautam@codeaurora.org From: Vivek Gautam To: joro@8bytes.org, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, robin.murphy@arm.com, will.deacon@arm.com, robdclark@gmail.com, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Cc: alex.williamson@redhat.com, gregkh@linuxfoundation.org, sboyd@codeaurora.org, sricharan@codeaurora.org, m.szyprowski@samsung.com, architt@codeaurora.org, airlied@linux.ie, linux-arm-msm@vger.kernel.org, vivek.gautam@codeaurora.org Subject: [PATCH v8 5/6] iommu/arm-smmu: Add support for qcom, smmu-v2 variant Date: Fri, 9 Feb 2018 16:27:06 +0530 Message-Id: <1518173826-11759-1-git-send-email-vivek.gautam@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517999482-17317-6-git-send-email-vivek.gautam@codeaurora.org> References: <1517999482-17317-6-git-send-email-vivek.gautam@codeaurora.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP qcom,smmu-v2 is an arm,smmu-v2 implementation with specific clock and power requirements. This smmu core is used with multiple masters on msm8996, viz. mdss, video, etc. Add bindings for the same. Signed-off-by: Vivek Gautam Reviewed-by: Rob Herring --- Changes in v8: - Added the missing IOMMU_OF_DECLARE declaration for "qcom,smmu-v2" .../devicetree/bindings/iommu/arm,smmu.txt | 43 ++++++++++++++++++++++ drivers/iommu/arm-smmu.c | 14 +++++++ 2 files changed, 57 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 8a6ffce12af5..169222ae2706 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -17,10 +17,19 @@ conditions. "arm,mmu-401" "arm,mmu-500" "cavium,smmu-v2" + "qcom,-smmu-v2", "qcom,smmu-v2" depending on the particular implementation and/or the version of the architecture implemented. + A number of Qcom SoCs use qcom,smmu-v2 version of the IP. + "qcom,-smmu-v2" represents a soc specific compatible + string that should be present along with the "qcom,smmu-v2" + to facilitate SoC specific clocks/power connections and to + address specific bug fixes. + An example string would be - + "qcom,msm8996-smmu-v2", "qcom,smmu-v2". + - reg : Base address and size of the SMMU. - #global-interrupts : The number of global interrupts exposed by the @@ -71,6 +80,23 @@ conditions. or using stream matching with #iommu-cells = <2>, and may be ignored if present in such cases. +- clock-names: Should be "bus", and "iface" for "qcom,smmu-v2" + implementation. + + "bus" clock for "qcom,smmu-v2" is required for downstream + bus access and for the smmu ptw. + + "iface" clock is required to access smmu's registers through + the TCU's programming interface. + +- clocks: Phandles for respective clocks described by clock-names. + +- power-domains: Phandles to SMMU's power domain specifier. This is + required even if SMMU belongs to the master's power + domain, as the SMMU will have to be enabled and + accessed before master gets enabled and linked to its + SMMU. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : @@ -137,3 +163,20 @@ conditions. iommu-map = <0 &smmu3 0 0x400>; ... }; + + /* Qcom's arm,smmu-v2 implementation */ + smmu4: iommu { + compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; + reg = <0xd00000 0x10000>; + + #global-interrupts = <1>; + interrupts = , + , + ; + #iommu-cells = <1>; + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc SMMU_MDP_AXI_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>; + clock-names = "bus", "iface"; + }; diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index c7e924d553bd..40da3f251acf 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -119,6 +119,7 @@ enum arm_smmu_implementation { GENERIC_SMMU, ARM_MMU500, CAVIUM_SMMUV2, + QCOM_SMMUV2, }; struct arm_smmu_s2cr { @@ -1950,6 +1951,17 @@ struct arm_smmu_match_data { ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500); ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2); +static const char * const qcom_smmuv2_clks[] = { + "bus", "iface", +}; + +static const struct arm_smmu_match_data qcom_smmuv2 = { + .version = ARM_SMMU_V2, + .model = QCOM_SMMUV2, + .clks = qcom_smmuv2_clks, + .num_clks = ARRAY_SIZE(qcom_smmuv2_clks), +}; + static const struct of_device_id arm_smmu_of_match[] = { { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 }, { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 }, @@ -1957,6 +1969,7 @@ struct arm_smmu_match_data { { .compatible = "arm,mmu-401", .data = &arm_mmu401 }, { .compatible = "arm,mmu-500", .data = &arm_mmu500 }, { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 }, + { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 }, { }, }; MODULE_DEVICE_TABLE(of, arm_smmu_of_match); @@ -2319,6 +2332,7 @@ static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev) IOMMU_OF_DECLARE(arm_mmu401, "arm,mmu-401"); IOMMU_OF_DECLARE(arm_mmu500, "arm,mmu-500"); IOMMU_OF_DECLARE(cavium_smmuv2, "cavium,smmu-v2"); +IOMMU_OF_DECLARE(qcom_smmuv2, "qcom,smmu-v2"); MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); MODULE_AUTHOR("Will Deacon ");