Message ID | 1537154264-23252-1-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
---|---|
State | Changes Requested, archived |
Headers | show
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Mon, 17 Sep 2018 03:23:04 +0000 From: Anson Huang <Anson.Huang@nxp.com> To: shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, fabio.estevam@nxp.com, robh+dt@kernel.org, mark.rutland@arm.com, rjw@rjwysocki.net, viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V2 1/2] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading Date: Mon, 17 Sep 2018 11:17:43 +0800 Message-Id: <1537154264-23252-1-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: HK0PR01CA0018.apcprd01.prod.exchangelabs.com (2603:1096:203:92::30) To AM0PR0402MB3906.eurprd04.prod.outlook.com (2603:10a6:208:f::26) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fc402f14-453e-4935-a8d5-08d61c4ce436 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(7020095)(4652040)(8989137)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(5600074)(711020)(4618075)(2017052603328)(7153060)(7193020);SRVR:AM0PR0402MB3906; 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[V2,1/2] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
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On Mon, Sep 17, 2018 at 11:17:43AM +0800, Anson Huang wrote: > On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock > needs to be enabled first, so use the nvmem-cells binding instead. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > --- > no change since V1. Okay, I just applied v1 of this patch. Shawn
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 5ef4320..ff8c6de 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -89,6 +89,8 @@ "pll1_sys"; arm-supply = <®_arm>; soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; }; @@ -943,6 +945,10 @@ tempmon_temp_grade: temp-grade@20 { reg = <0x20 4>; }; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; }; lcdif: lcdif@21c8000 {
On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first, so use the nvmem-cells binding instead. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- no change since V1. arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)