diff mbox series

[V2,1/2] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading

Message ID 1537154264-23252-1-git-send-email-Anson.Huang@nxp.com (mailing list archive)
State Changes Requested, archived
Headers show
Series [V2,1/2] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading | expand

Commit Message

Anson Huang Sept. 17, 2018, 3:17 a.m. UTC 
On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first, so use the nvmem-cells binding instead.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
no change since V1.
 arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Shawn Guo Sept. 26, 2018, 9:20 a.m. UTC | #1 
On Mon, Sep 17, 2018 at 11:17:43AM +0800, Anson Huang wrote:
> On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
> needs to be enabled first, so use the nvmem-cells binding instead.
> 
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> no change since V1.

Okay, I just applied v1 of this patch.

Shawn
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 5ef4320..ff8c6de 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -89,6 +89,8 @@ 
 				      "pll1_sys";
 			arm-supply = <&reg_arm>;
 			soc-supply = <&reg_soc>;
+			nvmem-cells = <&cpu_speed_grade>;
+			nvmem-cell-names = "speed_grade";
 		};
 	};
 
@@ -943,6 +945,10 @@ 
 				tempmon_temp_grade: temp-grade@20 {
 					reg = <0x20 4>;
 				};
+
+				cpu_speed_grade: speed-grade@10 {
+					reg = <0x10 4>;
+				};
 			};
 
 			lcdif: lcdif@21c8000 {