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Fri, 1 Feb 2019 16:47:18 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Date: Fri, 1 Feb 2019 17:46:47 +0100 Message-Id: <1549039612-28905-4-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSaUgUYRjum9nZHa2RcTV9yaPYEDRwtQz6yCizazAqC4tQIdecPFKzHS2z yCNLE9Ol09QyxFC2wmutRcrQzCPzDq202FpCsExqV8ooq3E2+vd8z/E+Ly8fTSrvUkvo+ORU XpusSVTJ7WX3O2b7fCE9LNLf9MsJ15fUUnjUOkHhivY+ChebP5K4v79OgXtzPinw6yx33GAe ofCXwrcUHm4ul2PLhXaES/pbCHyv/Y0CDz7bgseya+T4yac8Cs+N1MuCHLnpl2cVXIP+vJxr rMrkWj8/JLgigx5xlgbPUHm4/boYPjH+GK/1Wx9lHzdlMaKUVof08sq9WahpUQGyo4FdDVND TUQBsqeVbA2C7O5hSnpYEVQVGW2KBcHT11bZv0iloV4uCdUIZoZKFaIwHxnRaQsQTctZNRj1 R0XamT0J46OPSdFPslkkGHN084Oc2F0w1pVHiFjGekFusYUUswwbAq2TAVKXJ7zqO0+K2I7d DvnmB0icA2yLAkwDE0gybYbRB+JCInaCyU6DQsLu0HOp0La0AL35epvnFOR1G22eQHjSOUiJ vSTrA7XNfhK9ERrvDBEiDawDvJxyFGnyL7x4/xop0Qzkn1NKbm8wFA4QEnaB6rtXbcM5KDM0 2e55E8HX3m5Ch5aW/i+7hZAeufJpQlIsL6xM5o+rBU2SkJYcqz54JKkB/f1DPXOdX41oZii6 DbE0Ui1i6n7siVRSmmPCiaQ2BDSpcmaCE8IilUyM5kQGrz1yQJuWyAttyI2WqVyZkwtMEUo2 VpPKH+b5FF77TyVouyVZSH8drf+9rf6K7HZCQWVmR+iswb3McxCWW8PXqN8x/p2P4LTbN2v0 DaZ6a+XqoE2YC6paXJHDfIza3+gSGTGbml17JeRM8HSA17KF7wfX/uzKHfeRu4ztPNQ9Z973 PW4Hd2HMP/qF924PX517jseqD6d2mE3KyyOBhK6PS8vY8FytkglxmpUrSK2g+QPx2eqqPwMA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnkeLIzCtJLcpLzFFi42I5/e/4PV3xipAYg21tfBYbZ6xntbj+5Tmr xfwj51gt+h+/ZrY4f34Du8XZpjfsFrcaZCw2Pb7GavGx5x6rxeVdc9gsPvceYbSYcX4fk8Xa I3fZLS6ecrW43biCzeLwm3ZWi3/XNrI4CHq8v9HK7rFpVSebx+Yl9R4H3+1h8ujbsorR4/Mm uQC2KD2bovzSklSFjPziElulaEMLIz1DSws9IxNLPUNj81grI1MlfTublNSczLLUIn27BL2M t593MBYc5KuYsyi0gXErTxcjJ4eEgInEoi0b2boYuTiEBJYySlz9dosdIiEmMWnfdihbWOLP tS6ook+MEstXfWHtYuTgYBPQk9ixqhCkRkSgXqL/zSWwGmaBPmaJxuOLWUESwgK+Eo+nfWIB sVkEVCVa+j8zg/TyCnhJHHxlDDFfTuLmuU5mEJtTwFui4/F2RhBbCKhk1b8DzBMY+RYwMqxi FEktLc5Nzy020itOzC0uzUvXS87P3cQIjIxtx35u2cHY9S74EKMAB6MSD++GX0ExQqyJZcWV uYcYJTiYlUR4nbJCYoR4UxIrq1KL8uOLSnNSiw8xmgLdNJFZSjQ5Hxi1eSXxhqaG5haWhubG 5sZmFkrivOcNKqOEBNITS1KzU1MLUotg+pg4OKUaGGP/3Lmjpe785bPERu8Nsi8U5B/P+aEW 2jAhgEPS9dTM4tuR3d9ufQt6+3HWsi985q6LEv5nXLPsCWXeEr0++nSna/bHhR8LrszvlOLa 9y/wnqH+YZ1PzAdiNl31/Zt0du/SCTwxpmfXTBS5GP6mZvfMMrbXmWZXohfsXHPQaOWfwMe3 zh5qifmgxFKckWioxVxUnAgAsp6ClaICAAA= X-CMS-MailID: 20190201164719eucas1p106c8761eb4bff12a906b601a37bf58b5 X-Msg-Generator: CA X-RootMTR: 20190201164719eucas1p106c8761eb4bff12a906b601a37bf58b5 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190201164719eucas1p106c8761eb4bff12a906b601a37bf58b5 References: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index f1a4f56..1fc5152 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1323,6 +1323,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), +}; + static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), @@ -1465,7 +1476,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),