From patchwork Wed Jul 15 11:09:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 11664891 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E7C413B1 for ; Wed, 15 Jul 2020 11:11:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 70FCF20658 for ; Wed, 15 Jul 2020 11:11:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731803AbgGOLLQ (ORCPT ); Wed, 15 Jul 2020 07:11:16 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:3372 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731779AbgGOLLP (ORCPT ); Wed, 15 Jul 2020 07:11:15 -0400 X-IronPort-AV: E=Sophos;i="5.75,355,1589209200"; d="scan'208";a="51982045" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 15 Jul 2020 20:11:13 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 37C094006DF5; Wed, 15 Jul 2020 20:11:08 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Wolfram Sang , Rob Herring , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Jakub Kicinski , Mark Brown , Niklas , Zhang Rui , Wim Van Sebroeck , Guenter Roeck , Magnus Damm Cc: Daniel Lezcano , Amit Kucheria , Thomas Gleixner , Laurent Pinchart , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-spi@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Lad Prabhakar Subject: [PATCH 20/20] arm64: dts: renesas: r8a774e1: Add CAN[FD] support Date: Wed, 15 Jul 2020 12:09:10 +0100 Message-Id: <1594811350-14066-21-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594811350-14066-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <1594811350-14066-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add CAN[01] and CANFD support to RZ/G2H (R8A774E1) SoC specific dtsi. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 56 +++++++++++++++++++++-- 1 file changed, 53 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index b2fa1a60470c..001874af8cf2 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -34,6 +34,13 @@ clock-frequency = <0>; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cluster0_opp: opp_table0 { compatible = "operating-points-v2"; opp-shared; @@ -1139,17 +1146,60 @@ }; can0: can@e6c30000 { + compatible = "renesas,can-r8a774e1", + "renesas,rcar-gen3-can"; reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; - - /* placeholder */ }; can1: can@e6c38000 { + compatible = "renesas,can-r8a774e1", + "renesas,rcar-gen3-can"; reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; + }; - /* placeholder */ + canfd: can@e66c0000 { + compatible = "renesas,r8a774e1-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; }; pwm0: pwm@e6e30000 {