From patchwork Mon Oct 26 08:19:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11855995 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 214C6139F for ; Mon, 26 Oct 2020 08:19:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F0513223FD for ; Mon, 26 Oct 2020 08:19:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="lYmJ7AfI" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1771497AbgJZITh (ORCPT ); Mon, 26 Oct 2020 04:19:37 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:47255 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1770925AbgJZITg (ORCPT ); Mon, 26 Oct 2020 04:19:36 -0400 X-UUID: f5b2368875bc4694b2ab26bf9e84aa32-20201026 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ZvY3ebtojCqfX4voGnQGPEtZw2caPlgJvmfJsJzbufw=; b=lYmJ7AfIuj+qBf0saoPn8EXVMzy3ocbqyeAafQW1mcrXNb9i5wR61BTRJ4cFJd5rMmjvCAi+FiZ2s9Nj8/LTAq5GckXcMPpcWRiZEawQGLDlr3yyQav7mcJpPH04dXJqoWwB3GF8oo7y5UWhlRUtcb6K1mgrMkp3E2TCYa9v3so=; X-UUID: f5b2368875bc4694b2ab26bf9e84aa32-20201026 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 648784899; Mon, 26 Oct 2020 16:19:32 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Oct 2020 16:19:14 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Oct 2020 16:19:14 +0800 From: Hector Yuan To: , , , Rob Herring , Sudeep Holla , "Rafael J. Wysocki" , Viresh Kumar , Maxime Ripard , Santosh Shilimkar , Amit Kucheria , Stephen Boyd , Ulf Hansson , Dave Gerlach , Florian Fainelli , Robin Murphy , Lorenzo Pieralisi , CC: , , Subject: [PATCH v8 3/3] dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW Date: Mon, 26 Oct 2020 16:19:09 +0800 Message-ID: <1603700349-5922-4-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1603700349-5922-1-git-send-email-hector.yuan@mediatek.com> References: <1603700349-5922-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: F7CCB49E09000072F62F73DDE781F4FACB0C6ADFAD64C3EB4D0B72B91C61209A2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Hector.Yuan" Add devicetree bindings for MediaTek HW driver. Signed-off-by: Hector.Yuan --- .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 113 ++++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml new file mode 100644 index 0000000..32d2ad4 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek's CPUFREQ Bindings + +maintainers: + - Hector Yuan + +description: + CPUFREQ HW is a hardware engine used by MediaTek + SoCs to manage frequency in hardware. It is capable of controlling frequency + for multiple clusters. + +properties: + compatible: + const: mediatek,cpufreq-hw + + reg: + minItems: 1 + maxItems: 2 + description: | + Addresses and sizes for the memory of the HW bases in each frequency domain. + +required: + - compatible + - reg + +examples: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mediatek,freq-domain = <&cpufreq_hw 0>; + reg = <0x000>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mediatek,freq-domain = <&cpufreq_hw 0>; + reg = <0x100>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mediatek,freq-domain = <&cpufreq_hw 0>; + reg = <0x200>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mediatek,freq-domain = <&cpufreq_hw 0>; + reg = <0x300>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mediatek,freq-domain = <&cpufreq_hw 1>; + reg = <0x400>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + mediatek,freq-domain = <&cpufreq_hw 1>; + reg = <0x500>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + mediatek,freq-domain = <&cpufreq_hw 1>; + reg = <0x600>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a75"; + enable-method = "psci"; + mediatek,freq-domain = <&cpufreq_hw 1>; + reg = <0x700>; + }; + }; + + /* ... */ + + soc { + #address-cells = <2>; + #size-cells = <2>; + + cpufreq_hw: cpufreq@11bc00 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x11bc10 0 0x8c>, + <0 0x11bca0 0 0x8c>; + }; + };