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Fri, 22 Jan 2021 17:38:37 +0000 Subject: [PATCH 1/8] cpupower: Update msr_pstate union struct naming From: Nathan Fontenot To: rrichter@amd.com, shuah@kernel.org, linux-kernel@vger.kernel.org, trenn@suse.com, linux-pm@vger.kernel.org Date: Fri, 22 Jan 2021 11:38:35 -0600 Message-ID: <161133711513.59625.9843026563692886689.stgit@ethanol01c7-host.amd.com> In-Reply-To: <161133705833.59625.6935511700675018185.stgit@ethanol01c7-host.amd.com> References: <161133705833.59625.6935511700675018185.stgit@ethanol01c7-host.amd.com> User-Agent: StGit/0.17.1-dirty X-Originating-IP: [165.204.78.2] X-ClientProxiedBy: CH2PR17CA0030.namprd17.prod.outlook.com (2603:10b6:610:53::40) To SN6PR12MB4720.namprd12.prod.outlook.com (2603:10b6:805:e6::31) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from ethanol01c7-host.amd.com (165.204.78.2) by CH2PR17CA0030.namprd17.prod.outlook.com (2603:10b6:610:53::40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3784.11 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?utf-8?q?n6vIFIuyE1mFTuWM6gu89t/Vgs1+fy?= =?utf-8?q?QlCNR3koYGWw7/3zsOVx9lNFD/bK0oMDwEJMWIIoDiU14L6s2vlf+xCB+DPzxMoP8?= =?utf-8?q?ZGineHIWn3/C09XLJaOxp8QaORO2FgWXUZ44zBk6PjM2010UUSkQaoPrvLea9HR86?= =?utf-8?q?SRpDYAHUtPm6M1WFg0CupEmGk4aFqruhU/mtazGDR0NlokGTdLpTSqiQrM3K2EKhy?= =?utf-8?q?eB9dBoZL73S+PeAUkFehU2QgdOASQMYxOJeCUrWzZqyiNt+zh1hsWNFQo2MVMwYvF?= =?utf-8?q?ZE9kiEfH/gfncGaZIijtR3BVUFfqm7ezsJNFfXyjh73XL/UOtvdHShIa0s4kT2yjv?= =?utf-8?q?BsYikM+OhC8bMmK5bGowtRkW5mNXAEfQrwCUlgGj0BSifC2/WktTIqQ/9B+/Rybmc?= =?utf-8?q?nofDE8Kr9a9eX8AXE/6uWsRY84+eqIyB+sQIaUGvxIHa8nMiQgmzbPwSujQYZ/svw?= =?utf-8?q?AcFRzI+rrKQKAEUNDW0Cyl2vTUZcoJ7e+/29p4bDqNmJIcWaRS98TDygU1uvEYrcj?= =?utf-8?q?bUorCOJOjtO0WlZCf5SP47nXV6RQmnr9KNoLtLcxeKJoDz3QsG+/J0nKI73IDG09T?= =?utf-8?q?pVu9RWTO2lfvoZWGJM6Ew4/kAwcosqr45n9RUp9uoIZZ48rv8z53knPI1OiUXhpKS?= =?utf-8?q?RHiTE78GLmpmxM8ckF/WNs38i6i9G+N9zBgn4OFlaLO7ENcjN7XJs7W59olLctE/6?= =?utf-8?q?Fi13AHMdCT9QmyXB3t1qqOfhW+0FLlGjsUzkTk07wjlGSuuAyLqsqcxF196mbTXd3?= =?utf-8?q?34Ht/fnZl8zc7Kjeg8LnfejdVK9WKxiRTcVwYY1JmI62P8M4lbw/yMRKGYJw0bTaf?= =?utf-8?q?ivsTkjusVUMwsaO7n6aaEk3TbN5BjbegdgNK2dWxL/GuGLMutCbGCnQsHUAGubpXG?= =?utf-8?q?1uH+1/hE7nsoPhp7orUtD2AX9kEnrCAIa+l4eYLX6FeY6u2NdTgc5b8kScLT5hrn2?= =?utf-8?q?+a9ydSkXmnnHWrEd25uaC+dnS/Mwthu+4xLGpavCrKDe/ef/erufNXVK42XnMu9gF?= =?utf-8?q?Fkr4LxHdzqx1jvYPnj?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7edc9c06-8de1-4b9d-5b16-08d8befc8c85 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB4720.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2021 17:38:37.2480 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: q54u+i/JQQ1blm6/sJ+svKVF8dhUYFxDYW34Y5ScVGKzqm8rhBEbqKIUVBNXMDQcGiaZqB6LGTOJ0+9MHX2qSw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2846 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The msr_pstate union struct named fam17h_bits is misleading since this is the struct to use for all families >= 0x17, not just for family 0x17. Rename the bits structs to be 'pstate' (for pre family 17h CPUs) and 'pstatedef' (for CPUs since fam 17h) to align closer with PPR/BDKG naming. There are no functional changes as part of this update. Signed-off-by: Nathan Fontenot --- tools/power/cpupower/utils/helpers/amd.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/tools/power/cpupower/utils/helpers/amd.c b/tools/power/cpupower/utils/helpers/amd.c index 7c4f83a8c973..34368436bbd6 100644 --- a/tools/power/cpupower/utils/helpers/amd.c +++ b/tools/power/cpupower/utils/helpers/amd.c @@ -13,7 +13,8 @@ #define MSR_AMD_PSTATE 0xc0010064 #define MSR_AMD_PSTATE_LIMIT 0xc0010061 -union msr_pstate { +union core_pstate { + /* pre fam 17h: */ struct { unsigned fid:6; unsigned did:3; @@ -26,7 +27,8 @@ union msr_pstate { unsigned idddiv:2; unsigned res3:21; unsigned en:1; - } bits; + } pstate; + /* since fam 17h: */ struct { unsigned fid:8; unsigned did:6; @@ -35,36 +37,36 @@ union msr_pstate { unsigned idddiv:2; unsigned res1:31; unsigned en:1; - } fam17h_bits; + } pstatedef; unsigned long long val; }; -static int get_did(int family, union msr_pstate pstate) +static int get_did(int family, union core_pstate pstate) { int t; if (family == 0x12) t = pstate.val & 0xf; else if (family == 0x17 || family == 0x18) - t = pstate.fam17h_bits.did; + t = pstate.pstatedef.did; else - t = pstate.bits.did; + t = pstate.pstate.did; return t; } -static int get_cof(int family, union msr_pstate pstate) +static int get_cof(int family, union core_pstate pstate) { int t; int fid, did, cof; did = get_did(family, pstate); if (family == 0x17 || family == 0x18) { - fid = pstate.fam17h_bits.fid; + fid = pstate.pstatedef.fid; cof = 200 * fid / did; } else { t = 0x10; - fid = pstate.bits.fid; + fid = pstate.pstate.fid; if (family == 0x11) t = 0x8; cof = (100 * (fid + t)) >> did; @@ -89,7 +91,7 @@ int decode_pstates(unsigned int cpu, unsigned int cpu_family, int boost_states, unsigned long *pstates, int *no) { int i, psmax, pscur; - union msr_pstate pstate; + union core_pstate pstate; unsigned long long val; /* Only read out frequencies from HW when CPU might be boostable @@ -119,9 +121,9 @@ int decode_pstates(unsigned int cpu, unsigned int cpu_family, } if (read_msr(cpu, MSR_AMD_PSTATE + i, &pstate.val)) return -1; - if ((cpu_family == 0x17) && (!pstate.fam17h_bits.en)) + if ((cpu_family == 0x17) && (!pstate.pstatedef.en)) continue; - else if (!pstate.bits.en) + else if (!pstate.pstate.en) continue; pstates[i] = get_cof(cpu_family, pstate);