From patchwork Thu Jun 9 17:53:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Russell King - ARM Linux X-Patchwork-Id: 866372 Received: from smtp1.linux-foundation.org (smtp1.linux-foundation.org [140.211.169.13]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p59HtHfS025747 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=FAIL) for ; Thu, 9 Jun 2011 17:55:38 GMT Received: from daredevil.linux-foundation.org (localhost [127.0.0.1]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id p59HrXCX025700; Thu, 9 Jun 2011 10:53:34 -0700 Received: from caramon.arm.linux.org.uk (caramon.arm.linux.org.uk [78.32.30.218]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id p59HrRhk025684 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Thu, 9 Jun 2011 10:53:31 -0700 Received: from n2100.arm.linux.org.uk ([2002:4e20:1eda:1:214:fdff:fe10:4f86]) by caramon.arm.linux.org.uk with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.72) (envelope-from ) id 1QUjPv-0005cx-Bt; Thu, 09 Jun 2011 18:53:15 +0100 Received: from linux by n2100.arm.linux.org.uk with local (Exim 4.72) (envelope-from ) id 1QUjPu-0008Jc-3H; Thu, 09 Jun 2011 18:53:14 +0100 Date: Thu, 9 Jun 2011 18:53:13 +0100 From: Russell King - ARM Linux To: Santosh Shilimkar Message-ID: <20110609175313.GG24424@n2100.arm.linux.org.uk> References: <201106072348.44624.rjw@sisk.pl> <20110609154058.GA24424@n2100.arm.linux.org.uk> <4DF0F45A.3030103@ti.com> <20110609164024.GB24424@n2100.arm.linux.org.uk> <4DF0FA73.8050607@ti.com> <20110609171255.GD24424@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20110609171255.GD24424@n2100.arm.linux.org.uk> User-Agent: Mutt/1.5.19 (2009-01-05) Received-SPF: pass (localhost is always allowed.) X-Spam-Status: No, hits=-4.346 required=5 tests=AWL, BAYES_00, OSDL_HEADER_SUBJECT_BRACKETED X-Spam-Checker-Version: SpamAssassin 3.2.4-osdl_revision__1.47__ X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.21 Cc: Frank Hofmann , linux-pm@lists.linux-foundation.org, tuxonice-devel@tuxonice.net, linux-arm-kernel@lists.infradead.org Subject: Re: [linux-pm] [RFC PATCH v4] ARM hibernation/suspend-to-disk support X-BeenThere: linux-pm@lists.linux-foundation.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Linux power management List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-pm-bounces@lists.linux-foundation.org Errors-To: linux-pm-bounces@lists.linux-foundation.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Thu, 09 Jun 2011 17:55:38 +0000 (UTC) On Thu, Jun 09, 2011 at 06:12:55PM +0100, Russell King - ARM Linux wrote: > > 3. Avoid direct write to AUXCTRL in generic suspend code. > > This is the only problematical one that I can see. We need to restore > this on systems running in secure mode. What we could do is rather than > writing to the register, read it first and compare its value with what > was saved to see whether we need to write it. > > Then, if platforms run in non-secure mode, they are responsible for > restoring that register back to its pre-suspend value before their > assembly calls cpu_resume(). And here's a patch which does that: 8<----------- From: Russell King ARM: Avoid writing to auxctrl register unless it needs to be updated As the auxiliary control register is not writable in non-secure mode such as on OMAP, we must avoid writing the register when resuming in non-secure mode. Avoid this by moving the responsibility to the SoC code in this case to ensure that the auxiliary control register is restored before cpu_resume() is called. Signed-off-by: Russell King --- arch/arm/mm/proc-v7.S | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 3c38678..fa1e6d5 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -237,7 +237,9 @@ ENTRY(cpu_v7_do_resume) mcr p15, 0, r7, c2, c0, 0 @ TTB 0 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 mcr p15, 0, ip, c2, c0, 2 @ TTB control register - mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register + mrc p15, 0, r4, c1, c0, 1 @ Read auxiliary control register + teq r4, r10 + mcrne p15, 0, r10, c1, c0, 1 @ Auxiliary control register mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control ldr r4, =PRRR @ PRRR ldr r5, =NMRR @ NMRR