From patchwork Thu Oct 13 15:30:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piotr Luc X-Patchwork-Id: 9375163 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7746860839 for ; Thu, 13 Oct 2016 15:32:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 65F9A2A132 for ; Thu, 13 Oct 2016 15:32:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 58CC62A139; Thu, 13 Oct 2016 15:32:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6CFF22A132 for ; Thu, 13 Oct 2016 15:32:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756175AbcJMPbi (ORCPT ); Thu, 13 Oct 2016 11:31:38 -0400 Received: from mga06.intel.com ([134.134.136.31]:26433 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756084AbcJMPb0 (ORCPT ); Thu, 13 Oct 2016 11:31:26 -0400 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP; 13 Oct 2016 08:31:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,340,1473145200"; d="scan'208";a="19233637" Received: from gklab-125-115.igk.intel.com ([10.91.125.115]) by fmsmga006.fm.intel.com with ESMTP; 13 Oct 2016 08:31:22 -0700 From: Piotr Luc To: Mauro Carvalho Chehab , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, "Rafael J. Wysocki" , Viresh Kumar Cc: Doug Thompson , Borislav Petkov , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Len Brown , linux-pm@vger.kernel.org, Srinivas Pandruvada Subject: [PATCH v2 02/11] tools/power turbostat: Use Intel family processor macros Date: Thu, 13 Oct 2016 17:30:56 +0200 Message-Id: <20161013153105.2517-3-piotr.luc@intel.com> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161013153105.2517-1-piotr.luc@intel.com> References: <20161013153105.2517-1-piotr.luc@intel.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Use macros of Intel processor families instead of raw numbers. Signed-off-by: Piotr Luc Reviewed-by: Dave Hansen Cc: linux-kernel@vger.kernel.org --- v2: Include Intel family header. tools/power/x86/turbostat/Makefile | 3 +- tools/power/x86/turbostat/turbostat.c | 243 +++++++++++++++++----------------- 2 files changed, 124 insertions(+), 122 deletions(-) diff --git a/tools/power/x86/turbostat/Makefile b/tools/power/x86/turbostat/Makefile index 8561e7d..20631f6 100644 --- a/tools/power/x86/turbostat/Makefile +++ b/tools/power/x86/turbostat/Makefile @@ -9,7 +9,8 @@ endif turbostat : turbostat.c CFLAGS += -Wall -CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"' +CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"' \ + -DFAMILYHEADER='"../../../../arch/x86/include/asm/intel-family.h"' %: %.c @mkdir -p $(BUILD_OUTPUT) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 3e199b5..09a542cc 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -21,6 +21,7 @@ #define _GNU_SOURCE #include MSRHEADER +#include FAMILYHEADER #include #include #include @@ -2174,47 +2175,47 @@ int probe_nhm_msrs(unsigned int family, unsigned int model) bclk = discover_bclk(family, model); switch (model) { - case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ - case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ - case 0x1F: /* Core i7 and i5 Processor - Nehalem */ - case 0x25: /* Westmere Client - Clarkdale, Arrandale */ - case 0x2C: /* Westmere EP - Gulftown */ - case 0x2E: /* Nehalem-EX Xeon - Beckton */ - case 0x2F: /* Westmere-EX Xeon - Eagleton */ + case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ + case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ + case INTEL_FAM6_NEHALEM_G: /* Core i7 and i5 Processor - Nehalem */ + case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */ + case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */ + case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ + case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ pkg_cstate_limits = nhm_pkg_cstate_limits; break; - case 0x2A: /* SNB */ - case 0x2D: /* SNB Xeon */ - case 0x3A: /* IVB */ - case 0x3E: /* IVB Xeon */ + case INTEL_FAM6_SANDYBRIDGE: /* SNB */ + case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */ + case INTEL_FAM6_IVYBRIDGE: /* IVB */ + case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ pkg_cstate_limits = snb_pkg_cstate_limits; break; - case 0x3C: /* HSW */ - case 0x3F: /* HSX */ - case 0x45: /* HSW */ - case 0x46: /* HSW */ - case 0x3D: /* BDW */ - case 0x47: /* BDW */ - case 0x4F: /* BDX */ - case 0x56: /* BDX-DE */ - case 0x4E: /* SKL */ - case 0x5E: /* SKL */ - case 0x8E: /* KBL */ - case 0x9E: /* KBL */ - case 0x55: /* SKX */ + case INTEL_FAM6_HASWELL_CORE: /* HSW */ + case INTEL_FAM6_HASWELL_X: /* HSX */ + case INTEL_FAM6_HASWELL_ULT: /* HSW */ + case INTEL_FAM6_HASWELL_GT3E: /* HSW */ + case INTEL_FAM6_BROADWELL_CORE: /* BDW */ + case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ + case INTEL_FAM6_BROADWELL_X: /* BDX */ + case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ + case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ + case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ + case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ + case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ + case INTEL_FAM6_SKYLAKE_X: /* SKX */ pkg_cstate_limits = hsw_pkg_cstate_limits; break; - case 0x37: /* BYT */ - case 0x4D: /* AVN */ + case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ + case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ pkg_cstate_limits = slv_pkg_cstate_limits; break; - case 0x4C: /* AMT */ + case INTEL_FAM6_ATOM_AIRMONT: /* AMT */ pkg_cstate_limits = amt_pkg_cstate_limits; break; - case 0x57: /* PHI */ + case INTEL_FAM6_XEON_PHI_KNL: /* PHI */ pkg_cstate_limits = phi_pkg_cstate_limits; break; - case 0x5C: /* BXT */ + case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ pkg_cstate_limits = bxt_pkg_cstate_limits; break; default: @@ -2234,9 +2235,9 @@ int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) { switch (model) { /* Nehalem compatible, but do not include turbo-ratio limit support */ - case 0x2E: /* Nehalem-EX Xeon - Beckton */ - case 0x2F: /* Westmere-EX Xeon - Eagleton */ - case 0x57: /* PHI - Knights Landing (different MSR definition) */ + case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */ + case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */ + case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */ return 0; default: return 1; @@ -2251,8 +2252,8 @@ int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) return 0; switch (model) { - case 0x3E: /* IVB Xeon */ - case 0x3F: /* HSW Xeon */ + case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ + case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ return 1; default: return 0; @@ -2267,7 +2268,7 @@ int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) return 0; switch (model) { - case 0x3F: /* HSW Xeon */ + case INTEL_FAM6_HASWELL_X: /* HSW Xeon */ return 1; default: return 0; @@ -2283,7 +2284,7 @@ int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) return 0; switch (model) { - case 0x57: /* Knights Landing */ + case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ return 1; default: return 0; @@ -2298,22 +2299,22 @@ int has_config_tdp(unsigned int family, unsigned int model) return 0; switch (model) { - case 0x3A: /* IVB */ - case 0x3C: /* HSW */ - case 0x3F: /* HSX */ - case 0x45: /* HSW */ - case 0x46: /* HSW */ - case 0x3D: /* BDW */ - case 0x47: /* BDW */ - case 0x4F: /* BDX */ - case 0x56: /* BDX-DE */ - case 0x4E: /* SKL */ - case 0x5E: /* SKL */ - case 0x8E: /* KBL */ - case 0x9E: /* KBL */ - case 0x55: /* SKX */ - - case 0x57: /* Knights Landing */ + case INTEL_FAM6_IVYBRIDGE: /* IVB */ + case INTEL_FAM6_HASWELL_CORE: /* HSW */ + case INTEL_FAM6_HASWELL_X: /* HSX */ + case INTEL_FAM6_HASWELL_ULT: /* HSW */ + case INTEL_FAM6_HASWELL_GT3E: /* HSW */ + case INTEL_FAM6_BROADWELL_CORE: /* BDW */ + case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ + case INTEL_FAM6_BROADWELL_X: /* BDX */ + case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ + case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ + case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ + case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ + case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ + case INTEL_FAM6_SKYLAKE_X: /* SKX */ + + case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */ return 1; default: return 0; @@ -2593,8 +2594,8 @@ double get_tdp(unsigned int model) return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; switch (model) { - case 0x37: - case 0x4D: + case INTEL_FAM6_ATOM_SILVERMONT1: + case INTEL_FAM6_ATOM_SILVERMONT2: return 30.0; default: return 135.0; @@ -2611,10 +2612,10 @@ rapl_dram_energy_units_probe(int model, double rapl_energy_units) /* only called for genuine_intel, family 6 */ switch (model) { - case 0x3F: /* HSX */ - case 0x4F: /* BDX */ - case 0x56: /* BDX-DE */ - case 0x57: /* KNL */ + case INTEL_FAM6_HASWELL_X: /* HSX */ + case INTEL_FAM6_BROADWELL_X: /* BDX */ + case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ + case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ return (rapl_dram_energy_units = 15.3 / 1000000); default: return (rapl_energy_units); @@ -2640,37 +2641,37 @@ void rapl_probe(unsigned int family, unsigned int model) return; switch (model) { - case 0x2A: - case 0x3A: - case 0x3C: /* HSW */ - case 0x45: /* HSW */ - case 0x46: /* HSW */ - case 0x3D: /* BDW */ - case 0x47: /* BDW */ + case INTEL_FAM6_SANDYBRIDGE: + case INTEL_FAM6_IVYBRIDGE: + case INTEL_FAM6_HASWELL_CORE: /* HSW */ + case INTEL_FAM6_HASWELL_ULT: /* HSW */ + case INTEL_FAM6_HASWELL_GT3E: /* HSW */ + case INTEL_FAM6_BROADWELL_CORE: /* BDW */ + case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; break; - case 0x5C: /* BXT */ + case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO; break; - case 0x4E: /* SKL */ - case 0x5E: /* SKL */ - case 0x8E: /* KBL */ - case 0x9E: /* KBL */ + case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ + case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ + case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ + case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; break; - case 0x3F: /* HSX */ - case 0x4F: /* BDX */ - case 0x56: /* BDX-DE */ - case 0x55: /* SKX */ - case 0x57: /* KNL */ + case INTEL_FAM6_HASWELL_X: /* HSX */ + case INTEL_FAM6_BROADWELL_X: /* BDX */ + case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ + case INTEL_FAM6_SKYLAKE_X: /* SKX */ + case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; break; - case 0x2D: - case 0x3E: + case INTEL_FAM6_SANDYBRIDGE_X: + case INTEL_FAM6_IVYBRIDGE_X: do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; break; - case 0x37: /* BYT */ - case 0x4D: /* AVN */ + case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ + case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ do_rapl = RAPL_PKG | RAPL_CORES ; break; default: @@ -2713,11 +2714,11 @@ void perf_limit_reasons_probe(unsigned int family, unsigned int model) return; switch (model) { - case 0x3C: /* HSW */ - case 0x45: /* HSW */ - case 0x46: /* HSW */ + case INTEL_FAM6_HASWELL_CORE: /* HSW */ + case INTEL_FAM6_HASWELL_ULT: /* HSW */ + case INTEL_FAM6_HASWELL_GT3E: /* HSW */ do_gfx_perf_limit_reasons = 1; - case 0x3F: /* HSX */ + case INTEL_FAM6_HASWELL_X: /* HSX */ do_core_perf_limit_reasons = 1; do_ring_perf_limit_reasons = 1; default: @@ -2927,24 +2928,24 @@ int has_snb_msrs(unsigned int family, unsigned int model) return 0; switch (model) { - case 0x2A: - case 0x2D: - case 0x3A: /* IVB */ - case 0x3E: /* IVB Xeon */ - case 0x3C: /* HSW */ - case 0x3F: /* HSW */ - case 0x45: /* HSW */ - case 0x46: /* HSW */ - case 0x3D: /* BDW */ - case 0x47: /* BDW */ - case 0x4F: /* BDX */ - case 0x56: /* BDX-DE */ - case 0x4E: /* SKL */ - case 0x5E: /* SKL */ - case 0x8E: /* KBL */ - case 0x9E: /* KBL */ - case 0x55: /* SKX */ - case 0x5C: /* BXT */ + case INTEL_FAM6_SANDYBRIDGE: + case INTEL_FAM6_SANDYBRIDGE_X: + case INTEL_FAM6_IVYBRIDGE: /* IVB */ + case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */ + case INTEL_FAM6_HASWELL_CORE: /* HSW */ + case INTEL_FAM6_HASWELL_X: /* HSW */ + case INTEL_FAM6_HASWELL_ULT: /* HSW */ + case INTEL_FAM6_HASWELL_GT3E: /* HSW */ + case INTEL_FAM6_BROADWELL_CORE: /* BDW */ + case INTEL_FAM6_BROADWELL_GT3E: /* BDW */ + case INTEL_FAM6_BROADWELL_X: /* BDX */ + case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */ + case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ + case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ + case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ + case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ + case INTEL_FAM6_SKYLAKE_X: /* SKX */ + case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ return 1; } return 0; @@ -2968,13 +2969,13 @@ int has_hsw_msrs(unsigned int family, unsigned int model) return 0; switch (model) { - case 0x45: /* HSW */ - case 0x3D: /* BDW */ - case 0x4E: /* SKL */ - case 0x5E: /* SKL */ - case 0x8E: /* KBL */ - case 0x9E: /* KBL */ - case 0x5C: /* BXT */ + case INTEL_FAM6_HASWELL_ULT: /* HSW */ + case INTEL_FAM6_BROADWELL_CORE: /* BDW */ + case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ + case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ + case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ + case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ + case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ return 1; } return 0; @@ -2994,10 +2995,10 @@ int has_skl_msrs(unsigned int family, unsigned int model) return 0; switch (model) { - case 0x4E: /* SKL */ - case 0x5E: /* SKL */ - case 0x8E: /* KBL */ - case 0x9E: /* KBL */ + case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ + case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ + case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ + case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ return 1; } return 0; @@ -3010,8 +3011,8 @@ int is_slm(unsigned int family, unsigned int model) if (!genuine_intel) return 0; switch (model) { - case 0x37: /* BYT */ - case 0x4D: /* AVN */ + case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */ + case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */ return 1; } return 0; @@ -3022,7 +3023,7 @@ int is_knl(unsigned int family, unsigned int model) if (!genuine_intel) return 0; switch (model) { - case 0x57: /* KNL */ + case INTEL_FAM6_XEON_PHI_KNL: /* KNL */ return 1; } return 0; @@ -3303,16 +3304,16 @@ void process_cpuid() if (crystal_hz == 0) switch(model) { - case 0x4E: /* SKL */ - case 0x5E: /* SKL */ - case 0x8E: /* KBL */ - case 0x9E: /* KBL */ + case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */ + case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */ + case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */ + case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */ crystal_hz = 24000000; /* 24.0 MHz */ break; - case 0x55: /* SKX */ + case INTEL_FAM6_SKYLAKE_X: /* SKX */ crystal_hz = 25000000; /* 25.0 MHz */ break; - case 0x5C: /* BXT */ + case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */ crystal_hz = 19200000; /* 19.2 MHz */ break; default: