From patchwork Sat Jul 8 00:03:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Derek Basehore X-Patchwork-Id: 9831239 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 269C760352 for ; Sat, 8 Jul 2017 00:04:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1C2AE28578 for ; Sat, 8 Jul 2017 00:04:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 10E6C2858E; Sat, 8 Jul 2017 00:04:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE80228578 for ; Sat, 8 Jul 2017 00:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752658AbdGHADX (ORCPT ); Fri, 7 Jul 2017 20:03:23 -0400 Received: from mail-pg0-f47.google.com ([74.125.83.47]:33854 "EHLO mail-pg0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752631AbdGHADV (ORCPT ); Fri, 7 Jul 2017 20:03:21 -0400 Received: by mail-pg0-f47.google.com with SMTP id t186so24078968pgb.1 for ; Fri, 07 Jul 2017 17:03:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+6KIflXeEuwt5b1se+anHsHbRj+XWz33npqFk/MXOfQ=; b=gf+iqu5LkwOWELa0n31EeoBvKlU0G++vR1QsIIn/D1h8w2feqZTrkfbi9bgEyg8sY2 l8MDb3vNckCkN9N5gVp42r0eaSueAYapQz5qpDTGsyvhGt3FLOvvTbee0cPMhexI9E7/ qTdm61uRENXNp1V413vmrTrPljBC2LdRDvGKM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+6KIflXeEuwt5b1se+anHsHbRj+XWz33npqFk/MXOfQ=; b=KHhE0Rx+nlqNZ5vH0Jzt0XJDp7QOMSsKx7KeU5IhMm7aLFdkt1oxsP1KX2t8GTvv2O EOu3ewHBxr6lDrNXiaSsDoC+5Ui2GPNg1H7zGvZHBXjas2PAT+w6c3VXCc9gew8XzE09 bVRh7AmgbIdUy/kW64ck64Wq4jUMMVQsR+pG7mOl+IOGAYlwtjXQDfBVT+rYE6OprTJL yMaaLPwqcX3X4fjrFME4j/m2Ffp61nP+aFwB4BrsxTl9hl4mpTjBo5EASoFA+f8Js/LE reGN06ZlK9YNXaNr2DnXy5+z66EOGZ6pm0Gv2plYrqoRUU7LBWGgIbEWxadfHAFOJUR8 wN4A== X-Gm-Message-State: AIVw110G6KW4JE4sbZN0RofL5saQjhS+Ow1+D37R1etFBKFit+CYDCjx avl3n5uLXvfATHJc X-Received: by 10.84.232.3 with SMTP id h3mr5751228plk.42.1499472200882; Fri, 07 Jul 2017 17:03:20 -0700 (PDT) Received: from ketosis.mtv.corp.google.com ([172.22.65.104]) by smtp.gmail.com with ESMTPSA id p11sm10026278pfk.128.2017.07.07.17.03.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 07 Jul 2017 17:03:20 -0700 (PDT) From: Derek Basehore To: linux-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Rajneesh Bhardwaj , x86@kernel.org, platform-driver-x86@vger.kernel.org, "Rafael J . Wysocki" , Len Brown , linux-pm@vger.kernel.org, Derek Basehore Subject: [PATCH v5 3/5] x86, apic: Add freeze event support Date: Fri, 7 Jul 2017 17:03:01 -0700 Message-Id: <20170708000303.21863-3-dbasehore@chromium.org> X-Mailer: git-send-email 2.13.2.725.g09c95d1e9-goog In-Reply-To: <20170708000303.21863-1-dbasehore@chromium.org> References: <20170708000303.21863-1-dbasehore@chromium.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds support to the clock event devices created by apic to use freeze events. The apic is able to run a timer during freeze with near zero power impact on modern CPUs such as skylake. This will allow S0ix, suspend-to-idle, to be validated on Intel CPUs that support it. This is needed because bugs with power settings on the SoC can prevent S0ix entry. There is also no way to check this before idling all of the CPUs. Signed-off-by: Derek Basehore --- arch/x86/kernel/apic/apic.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 98b3dd8cf2bf..adc69d2f11ce 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -480,6 +480,26 @@ static int lapic_next_deadline(unsigned long delta, return 0; } +static int lapic_event_expired(struct clock_event_device *evt) +{ + u32 cct; + + cct = apic_read(APIC_TMCCT); + return cct == 0 ? 1 : 0; +} + +static int lapic_deadline_expired(struct clock_event_device *evt) +{ + u64 msr; + + /* + * When the timer interrupt is triggered, the register is cleared, so a + * non-zero value indicates a pending timer event. + */ + rdmsrl(MSR_IA32_TSC_DEADLINE, msr); + return msr == 0 ? 1 : 0; +} + static int lapic_timer_shutdown(struct clock_event_device *evt) { unsigned int v; @@ -534,7 +554,8 @@ static struct clock_event_device lapic_clockevent = { .name = "lapic", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP - | CLOCK_EVT_FEAT_DUMMY, + | CLOCK_EVT_FEAT_DUMMY + | CLOCK_EVT_FEAT_FREEZE_NONSTOP, .shift = 32, .set_state_shutdown = lapic_timer_shutdown, .set_state_periodic = lapic_timer_set_periodic, @@ -644,6 +665,7 @@ static void setup_APIC_timer(void) levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_DUMMY); levt->set_next_event = lapic_next_deadline; + levt->event_expired = lapic_deadline_expired; clockevents_config_and_register(levt, tsc_khz * (1000 / TSC_DIVISOR), 0xF, ~0UL);