From patchwork Thu Dec 14 10:30:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10111765 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EC649602C2 for ; Thu, 14 Dec 2017 10:30:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D3CDD212DB for ; Thu, 14 Dec 2017 10:30:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C88152936A; Thu, 14 Dec 2017 10:30:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C1FDB212DB for ; Thu, 14 Dec 2017 10:30:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751466AbdLNKaX (ORCPT ); Thu, 14 Dec 2017 05:30:23 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:57124 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751297AbdLNKaW (ORCPT ); Thu, 14 Dec 2017 05:30:22 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id 2A2622092C; Thu, 14 Dec 2017 11:30:20 +0100 (CET) Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id B21D2207A7; Thu, 14 Dec 2017 11:30:19 +0100 (CET) From: Miquel Raynal To: Zhang Rui , Eduardo Valentin , Rob Herring , Mark Rutland , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Catalin Marinas , Will Deacon Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Miquel Raynal , Baruch Siach , David Sniatkiwicz Subject: [PATCH v3 01/11] dt-bindings: thermal: Describe Armada AP806 and CP110 Date: Thu, 14 Dec 2017 11:30:01 +0100 Message-Id: <20171214103011.24713-2-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171214103011.24713-1-miquel.raynal@free-electrons.com> References: <20171214103011.24713-1-miquel.raynal@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Baruch Siach Add compatible strings for AP806 and CP110 that are part of the Armada 8k/7k line of SoCs. Add a note on the differences in the size of the control area in different bindings. This is an existing difference between the Armada 375 binding and the other boards already supported. The new AP806 and CP110 bindings are similar to the existing Armada 375 in this regard. Also add a note about the new property "marvell,thermal-zone-name" to help identify the zones from the sysfs. Signed-off-by: Baruch Siach [: reword, additional details, new property] Signed-off-by: Miquel Raynal --- .../devicetree/bindings/thermal/armada-thermal.txt | 29 ++++++++++++++++++---- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt index 24aacf8948c5..1602dc2ee220 100644 --- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt @@ -7,17 +7,36 @@ Required properties: marvell,armada375-thermal marvell,armada380-thermal marvell,armadaxp-thermal + marvell,armada-ap806-thermal + marvell,armada-cp110-thermal - reg: Device's register space. Two entries are expected, see the examples below. - The first one is required for the sensor register; - the second one is required for the control register - to be used for sensor initialization (a.k.a. calibration). + The first one points to the status register (4B). + The second one points to the control registers (8B). + Note: with legacy bindings, the second entry pointed + only on the so called "control MSB" ("control 1"), was + 4B wide and did not let the possibility to reach the + "control LSB" ("control 0") register. -Example: +Optional properties: +- marvell,thermal-zone-name: The name to identify the thermal zone + within the sysfs, useful when multiple + thermal zones are registered (AP, CPx...). + +Examples: + + /* Legacy bindings */ thermal@d0018300 { compatible = "marvell,armada370-thermal"; - reg = <0xd0018300 0x4 + reg = <0xd0018300 0x4 0xd0018304 0x4>; }; + + ap_thermal: thermal@6f8084 { + compatible = "marvell,armada-ap806-thermal"; + reg = <0x6f808C 0x4>, + <0x6f8084 0x8>; + marvell,thermal-zone-name = "ap_thermal_zone"; + };