From patchwork Thu Dec 14 10:30:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10111783 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3DF80602C2 for ; Thu, 14 Dec 2017 10:30:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 256D929B0B for ; Thu, 14 Dec 2017 10:30:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 19EEE29BB3; Thu, 14 Dec 2017 10:30:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6E9029B0B for ; Thu, 14 Dec 2017 10:30:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751341AbdLNKay (ORCPT ); Thu, 14 Dec 2017 05:30:54 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:57164 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751462AbdLNKaX (ORCPT ); Thu, 14 Dec 2017 05:30:23 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id BBA2820956; Thu, 14 Dec 2017 11:30:21 +0100 (CET) Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 5126E20758; Thu, 14 Dec 2017 11:30:21 +0100 (CET) From: Miquel Raynal To: Zhang Rui , Eduardo Valentin , Rob Herring , Mark Rutland , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Catalin Marinas , Will Deacon Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Miquel Raynal , Baruch Siach , David Sniatkiwicz Subject: [PATCH v3 05/11] thermal: armada: Add support for Armada AP806 Date: Thu, 14 Dec 2017 11:30:05 +0100 Message-Id: <20171214103011.24713-6-miquel.raynal@free-electrons.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171214103011.24713-1-miquel.raynal@free-electrons.com> References: <20171214103011.24713-1-miquel.raynal@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Baruch Siach The AP806 component is integrated in the Armada 8k and 7k lines of processors. The thermal sensor sample field on the status register is a signed value. Extend armada_get_temp() to handle signed values. Signed-off-by: Baruch Siach Signed-off-by: Miquel Raynal --- drivers/thermal/armada_thermal.c | 51 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c index e5b184cee79b..279d01937bb8 100644 --- a/drivers/thermal/armada_thermal.c +++ b/drivers/thermal/armada_thermal.c @@ -47,6 +47,11 @@ #define CONTROL0_OFFSET 0x0 #define CONTROL1_OFFSET 0x4 +/* TSEN refers to the temperature sensors within the AP */ +#define CONTROL0_TSEN_START BIT(0) +#define CONTROL0_TSEN_RESET BIT(1) +#define CONTROL0_TSEN_ENABLE BIT(2) + struct armada_thermal_data; /* Marvell EBU Thermal Sensor Dev Structure */ @@ -70,6 +75,7 @@ struct armada_thermal_data { unsigned long coef_m; unsigned long coef_div; bool inverted; + bool signed_sample; /* Register shift and mask to access the sensor temperature */ unsigned int temp_shift; @@ -154,6 +160,24 @@ static void armada380_init_sensor(struct platform_device *pdev, } } +static void armada_ap806_init_sensor(struct platform_device *pdev, + struct armada_thermal_priv *priv) +{ + u32 reg; + + if (!priv->control0) { + dev_err(&pdev->dev, + "Cannot access to control0 (control LSB) register\n"); + return; + } + + reg = readl_relaxed(priv->control0); + reg &= ~CONTROL0_TSEN_RESET; + reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE; + writel(reg, priv->control0); + msleep(10); +} + static bool armada_is_valid(struct armada_thermal_priv *priv) { u32 reg = readl_relaxed(priv->status); @@ -167,6 +191,7 @@ static int armada_get_temp(struct thermal_zone_device *thermal, struct armada_thermal_priv *priv = thermal->devdata; u32 reg; unsigned long m, b, div; + int sample; /* Valid check */ if (priv->data->is_valid && !priv->data->is_valid(priv)) { @@ -177,6 +202,11 @@ static int armada_get_temp(struct thermal_zone_device *thermal, reg = readl_relaxed(priv->status); reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask; + if (priv->data->signed_sample) + /* The most significant bit is the sign bit */ + sample = sign_extend32(reg, fls(priv->data->temp_mask) - 1); + else + sample = reg; /* Get formula coeficients */ b = priv->data->coef_b; @@ -184,9 +214,9 @@ static int armada_get_temp(struct thermal_zone_device *thermal, div = priv->data->coef_div; if (priv->data->inverted) - *temp = ((m * reg) - b) / div; + *temp = ((m * sample) - b) / div; else - *temp = (b - (m * reg)) / div; + *temp = (b - (m * sample)) / div; return 0; } @@ -237,6 +267,19 @@ static const struct armada_thermal_data armada380_data = { .inverted = true, }; +static const struct armada_thermal_data armada_ap806_data = { + .is_valid = armada_is_valid, + .init_sensor = armada_ap806_init_sensor, + .is_valid_bit = BIT(16), + .temp_shift = 0, + .temp_mask = 0x3ff, + .coef_b = -150000, + .coef_m = 423UL, + .coef_div = 1, + .inverted = true, + .signed_sample = true, +}; + static const struct of_device_id armada_thermal_id_table[] = { { .compatible = "marvell,armadaxp-thermal", @@ -255,6 +298,10 @@ static const struct of_device_id armada_thermal_id_table[] = { .data = &armada380_data, }, { + .compatible = "marvell,armada-ap806-thermal", + .data = &armada_ap806_data, + }, + { /* sentinel */ }, };