From patchwork Sat Feb 3 01:24:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Derek Basehore X-Patchwork-Id: 10198267 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6F08960467 for ; Sat, 3 Feb 2018 01:25:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 608B128E5C for ; Sat, 3 Feb 2018 01:25:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4D18F28FC4; Sat, 3 Feb 2018 01:25:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6831F28FC3 for ; Sat, 3 Feb 2018 01:25:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752177AbeBCBZM (ORCPT ); Fri, 2 Feb 2018 20:25:12 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:44756 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752446AbeBCBZB (ORCPT ); Fri, 2 Feb 2018 20:25:01 -0500 Received: by mail-pl0-f67.google.com with SMTP id f8so7474254plk.11 for ; Fri, 02 Feb 2018 17:25:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TgKuQio5vaCX+XiLgsu0GCVHobPEdTc/jPrTD507AWw=; b=ID09U5mYM2hbLDCqyzlnssOszKw+Q5LS6JjtDv5GuOr6gUli7e6l1a41zQcfIWx6Ly 4QEEXm9nu7hsDytCu3YpXafTcTe5XAyJNmUXvosxJ0pbSVEW59hdSvOpxjQN9Sq4T/lI ZPwZndSGpyn4OU8bu0YwWItyG0ylBWaKTTnv0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TgKuQio5vaCX+XiLgsu0GCVHobPEdTc/jPrTD507AWw=; b=HTgnepzXOSobEpafI/oEpTx8eirI8xg+sA3EBnFEA8rKFA3w/jd0fID3XNzd7sWlgD a3AwUYIvBgYyBJ7XASAmdnK0q+KfuRLoIbOVKPMQS+VlYy4QwFKu4Rb1QkY8ZKBp5uqr cS7Fp2+pijGX339JCE8lLrOuDoJOMeOJugyMPxH0eFRVsvGxaaQxOMjaEnQi79C2qTpn z19DhlxuqyYhTqVHjKt9Qo01o06xJOafrxTG5VgkciGdebuFlW6YO8tRZBO/dIOsoDJm eclN7Ed9zs7r9SFamXowj1RykCbpDR5nOsTT2aA/MaUpdPaksVvRJ3kmFPvxdgCqFQ78 mQEA== X-Gm-Message-State: AKwxytf4lV3upsVFcj1Yu88xKZ6YHj45gN/rqEW5YrDhPSxTxVD6he6+ BsvMnPLoeZ0zx1JkDp3Hv766Qw== X-Google-Smtp-Source: AH8x224If9SCIkBCqQu6raVcynurcmigU8MVIwMs1Pd97FC3a6cu/10+2Jsy3o0G9NaxoBZPh6UX2g== X-Received: by 2002:a17:902:1e5:: with SMTP id b92-v6mr37296893plb.144.1517621100721; Fri, 02 Feb 2018 17:25:00 -0800 (PST) Received: from exogeni.mtv.corp.google.com ([2620:0:1000:1600:211e:5908:95bc:4888]) by smtp.gmail.com with ESMTPSA id x124sm5332917pfx.105.2018.02.02.17.24.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Feb 2018 17:24:59 -0800 (PST) From: Derek Basehore To: linux-kernel@vger.kernel.org Cc: Soby.Mathew@arm.com, sudeep.holla@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-pm@vger.kernel.org, rafael.j.wysocki@intel.com, tglx@linutronix.de, briannorris@chromium.org, marc.zyngier@arm.com, Derek Basehore Subject: [PATCH v4 4/5] irqchip/gic-v3-its: add ability to resend MAPC on resume Date: Fri, 2 Feb 2018 17:24:49 -0800 Message-Id: <20180203012450.18378-5-dbasehore@chromium.org> X-Mailer: git-send-email 2.16.0.rc1.238.g530d649a79-goog In-Reply-To: <20180203012450.18378-1-dbasehore@chromium.org> References: <20180203012450.18378-1-dbasehore@chromium.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds functionality to resend the MAPC command to an ITS node on resume. If the ITS is powered down during suspend and the collections are not backed by memory, the ITS will lose that state. This just sets up the known state for the collections after the ITS is restored. This feature is enabled via Kconfig and a device tree entry. Signed-off-by: Derek Basehore --- arch/arm64/Kconfig | 10 ++++ drivers/irqchip/irq-gic-v3-its.c | 101 ++++++++++++++++++++++++--------------- 2 files changed, 73 insertions(+), 38 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 53612879fe56..f38f1a7b4266 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -571,6 +571,16 @@ config HISILICON_ERRATUM_161600802 If unsure, say Y. +config ARM_GIC500_COLLECTIONS_RESET + bool "GIC-500 Collections: Workaround for GIC-500 Collections on suspend reset" + default y + help + The GIC-500 can store Collections state internally for the ITS. If + the ITS is reset on suspend (ie from power getting disabled), the + collections need to be reconfigured on resume. + + If unsure, say Y. + config QCOM_FALKOR_ERRATUM_E1041 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" default y diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e13515cdb68f..63764efa4dcc 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -48,6 +48,7 @@ #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) #define ITS_FLAGS_SAVE_SUSPEND_STATE (1ULL << 3) +#define ITS_FLAGS_WORKAROUND_GIC500_MAPC (1ULL << 4) #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) @@ -1950,52 +1951,53 @@ static void its_cpu_init_lpis(void) dsb(sy); } -static void its_cpu_init_collection(void) +static void its_cpu_init_collection(struct its_node *its) { - struct its_node *its; - int cpu; - - spin_lock(&its_lock); - cpu = smp_processor_id(); - - list_for_each_entry(its, &its_nodes, entry) { - u64 target; + int cpu = smp_processor_id(); + u64 target; - /* avoid cross node collections and its mapping */ - if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { - struct device_node *cpu_node; + /* avoid cross node collections and its mapping */ + if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { + struct device_node *cpu_node; - cpu_node = of_get_cpu_node(cpu, NULL); - if (its->numa_node != NUMA_NO_NODE && - its->numa_node != of_node_to_nid(cpu_node)) - continue; - } + cpu_node = of_get_cpu_node(cpu, NULL); + if (its->numa_node != NUMA_NO_NODE && + its->numa_node != of_node_to_nid(cpu_node)) + return; + } + /* + * We now have to bind each collection to its target + * redistributor. + */ + if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { /* - * We now have to bind each collection to its target + * This ITS wants the physical address of the * redistributor. */ - if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { - /* - * This ITS wants the physical address of the - * redistributor. - */ - target = gic_data_rdist()->phys_base; - } else { - /* - * This ITS wants a linear CPU number. - */ - target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); - target = GICR_TYPER_CPU_NUMBER(target) << 16; - } + target = gic_data_rdist()->phys_base; + } else { + /* This ITS wants a linear CPU number. */ + target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER); + target = GICR_TYPER_CPU_NUMBER(target) << 16; + } - /* Perform collection mapping */ - its->collections[cpu].target_address = target; - its->collections[cpu].col_id = cpu; + /* Perform collection mapping */ + its->collections[cpu].target_address = target; + its->collections[cpu].col_id = cpu; - its_send_mapc(its, &its->collections[cpu], 1); - its_send_invall(its, &its->collections[cpu]); - } + its_send_mapc(its, &its->collections[cpu], 1); + its_send_invall(its, &its->collections[cpu]); +} + +static void its_cpu_init_collections(void) +{ + struct its_node *its; + + spin_lock(&its_lock); + + list_for_each_entry(its, &its_nodes, entry) + its_cpu_init_collection(its); spin_unlock(&its_lock); } @@ -2997,6 +2999,18 @@ static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data) return true; } +static bool __maybe_unused its_enable_quirk_gic500_collections(void *data) +{ + struct its_node *its = data; + + if (fwnode_property_present(its->fwnode_handle, + "collections-reset-on-suspend")) { + its->flags |= ITS_FLAGS_WORKAROUND_GIC500_MAPC; + return true; + } + return false; +} + static const struct gic_quirk its_quirks[] = { #ifdef CONFIG_CAVIUM_ERRATUM_22375 { @@ -3042,6 +3056,14 @@ static const struct gic_quirk its_quirks[] = { .mask = 0xffffffff, .init = its_enable_quirk_hip07_161600802, }, +#endif +#ifdef CONFIG_ARM_GIC500_COLLECTIONS_RESET + { + .desc = "ITS: GIC-500 Collections Reset on Resume", + .iidr = 0x00000000, + .mask = 0xff000000, + .init = its_enable_quirk_gic500_collections, + }, #endif { } @@ -3129,6 +3151,9 @@ static void its_restore_enable(void) } writel_relaxed(ctx->ctlr, base + GITS_CTLR); } + + if (its->flags & ITS_FLAGS_WORKAROUND_GIC500_MAPC) + its_cpu_init_collection(its); } spin_unlock(&its_lock); } @@ -3395,7 +3420,7 @@ int its_cpu_init(void) return -ENXIO; } its_cpu_init_lpis(); - its_cpu_init_collection(); + its_cpu_init_collections(); } return 0;