From patchwork Sat Apr 21 15:12:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10354221 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D2785600F6 for ; Sat, 21 Apr 2018 15:13:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C0FA8288C9 for ; Sat, 21 Apr 2018 15:13:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B512E288E8; Sat, 21 Apr 2018 15:13:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 63437288C9 for ; Sat, 21 Apr 2018 15:13:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753234AbeDUPNf (ORCPT ); Sat, 21 Apr 2018 11:13:35 -0400 Received: from mail.bootlin.com ([62.4.15.54]:60452 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753199AbeDUPNa (ORCPT ); Sat, 21 Apr 2018 11:13:30 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 49153207D2; Sat, 21 Apr 2018 17:13:29 +0200 (CEST) Received: from localhost.localdomain (unknown [91.224.148.103]) by mail.bootlin.com (Postfix) with ESMTPSA id 4900E207DB; Sat, 21 Apr 2018 17:13:18 +0200 (CEST) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Zhang Rui , Eduardo Valentin Cc: Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Antoine Tenart , Maxime Chevallier , Nadav Haklai , David Sniatkiwicz , Miquel Raynal Subject: [PATCH 21/27] arm64: dts: marvell: rename ap806 syscon node Date: Sat, 21 Apr 2018 17:12:49 +0200 Message-Id: <20180421151255.29929-22-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180421151255.29929-1-miquel.raynal@bootlin.com> References: <20180421151255.29929-1-miquel.raynal@bootlin.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In CP files, the syscons are called CP110_LABEL(syscon) in case of future additions. Use the same logic here to prepare the addition of a second syscon to access both the thermal IP, the DFX server registers and later probably other registers within this same memory area. Signed-off-by: Miquel Raynal --- .../devicetree/bindings/arm/marvell/ap806-system-controller.txt | 2 +- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt index c95f3ac5c728..3e1ceba1ab84 100644 --- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt @@ -79,7 +79,7 @@ Required properties: - offset: offset address inside the syscon block Example: -ap_syscon: system-controller@6f4000 { +ap_syscon0: system-controller@6f4000 { compatible = "syscon", "simple-mfd"; reg = <0x6f4000 0x1000>; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index ebda3edeceed..71208aba4468 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -238,7 +238,7 @@ status = "disabled"; }; - ap_syscon: system-controller@6f4000 { + ap_syscon0: system-controller@6f4000 { compatible = "syscon", "simple-mfd"; reg = <0x6f4000 0x2000>;