From patchwork Sat Apr 21 15:12:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 10354197 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5991D60231 for ; Sat, 21 Apr 2018 15:13:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47907288C9 for ; Sat, 21 Apr 2018 15:13:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3BC05288DB; Sat, 21 Apr 2018 15:13:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D74E0288C9 for ; Sat, 21 Apr 2018 15:13:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753177AbeDUPNU (ORCPT ); Sat, 21 Apr 2018 11:13:20 -0400 Received: from mail.bootlin.com ([62.4.15.54]:60373 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752783AbeDUPNQ (ORCPT ); Sat, 21 Apr 2018 11:13:16 -0400 Received: by mail.bootlin.com (Postfix, from userid 110) id 31CA5209A5; Sat, 21 Apr 2018 17:13:14 +0200 (CEST) Received: from localhost.localdomain (unknown [91.224.148.103]) by mail.bootlin.com (Postfix) with ESMTPSA id 30AEB207BE; Sat, 21 Apr 2018 17:13:03 +0200 (CEST) From: Miquel Raynal To: Gregory Clement , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Zhang Rui , Eduardo Valentin Cc: Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni , Antoine Tenart , Maxime Chevallier , Nadav Haklai , David Sniatkiwicz , Miquel Raynal Subject: [PATCH 06/27] thermal: armada: average over samples to avoid glitches Date: Sat, 21 Apr 2018 17:12:34 +0200 Message-Id: <20180421151255.29929-7-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180421151255.29929-1-miquel.raynal@bootlin.com> References: <20180421151255.29929-1-miquel.raynal@bootlin.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Configure the sample frequency and number of averaged samples. This is needed for two reasons: 1/ To be bootloader independent. 2/ To prepare the introduction of multi-sensors support by preventing inconsistencies when reading temperatures that could be a mean of samples took from different sensors. Signed-off-by: Miquel Raynal --- drivers/thermal/armada_thermal.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c index 9291ea3ad2f7..1f9706d96a0d 100644 --- a/drivers/thermal/armada_thermal.c +++ b/drivers/thermal/armada_thermal.c @@ -54,7 +54,12 @@ #define CONTROL0_TSEN_START BIT(0) #define CONTROL0_TSEN_RESET BIT(1) #define CONTROL0_TSEN_ENABLE BIT(2) +#define CONTROL0_TSEN_AVG_BYPASS BIT(6) +#define CONTROL0_TSEN_OSR_SHIFT 24 +#define CONTROL0_TSEN_OSR_MAX 0x3 +#define CONTROL1_TSEN_AVG_SHIFT 0 +#define CONTROL1_TSEN_AVG_MASK 0x7 #define CONTROL1_EXT_TSEN_SW_RESET BIT(7) #define CONTROL1_EXT_TSEN_HW_RESETn BIT(8) @@ -194,6 +199,13 @@ static void armada_ap806_init(struct platform_device *pdev, reg = readl_relaxed(priv->control0); reg &= ~CONTROL0_TSEN_RESET; reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE; + + /* Sample every ~2ms */ + reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT; + + /* Enable average (2 samples by default) */ + reg &= ~CONTROL0_TSEN_AVG_BYPASS; + writel(reg, priv->control0); /* Wait the sensors to be valid or the core will warn the user */ @@ -203,7 +215,20 @@ static void armada_ap806_init(struct platform_device *pdev, static void armada_cp110_init(struct platform_device *pdev, struct armada_thermal_priv *priv) { + u32 reg; + armada380_init(pdev, priv); + + /* Sample every ~2ms */ + reg = readl_relaxed(priv->control0); + reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT; + writel(reg, priv->control0); + + /* Average the output value over 2^1 = 2 samples */ + reg = readl_relaxed(priv->control1); + reg &= ~CONTROL1_TSEN_AVG_MASK << CONTROL1_TSEN_AVG_SHIFT; + reg |= 1 << CONTROL1_TSEN_AVG_SHIFT; + writel(reg, priv->control1); } static bool armada_is_valid(struct armada_thermal_priv *priv)