From patchwork Wed Feb 6 18:12:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Ferre X-Patchwork-Id: 10799843 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B57081575 for ; Wed, 6 Feb 2019 18:13:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A6BCA2CF67 for ; Wed, 6 Feb 2019 18:13:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 95E052CF91; Wed, 6 Feb 2019 18:13:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 397732CF67 for ; Wed, 6 Feb 2019 18:13:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727907AbfBFSMy (ORCPT ); Wed, 6 Feb 2019 13:12:54 -0500 Received: from esa3.microchip.iphmx.com ([68.232.153.233]:40479 "EHLO esa3.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728260AbfBFSMy (ORCPT ); Wed, 6 Feb 2019 13:12:54 -0500 X-IronPort-AV: E=Sophos;i="5.56,564,1539673200"; d="scan'208";a="26383921" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 06 Feb 2019 11:12:31 -0700 Received: from tenerife.corp.atmel.com (10.10.76.4) by chn-sv-exch04.mchp-main.com (10.10.76.105) with Microsoft SMTP Server id 14.3.352.0; Wed, 6 Feb 2019 11:12:31 -0700 From: Nicolas Ferre To: Alexandre Belloni , Ludovic Desroches , , Sebastian Reichel CC: , , Nicolas Ferre Subject: [PATCH v2 2/3] dt-bindings: arm: atmel: add new sam9x60 reset controller binding Date: Wed, 6 Feb 2019 19:12:20 +0100 Message-ID: <20190206181221.27914-2-nicolas.ferre@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190206181221.27914-1-nicolas.ferre@microchip.com> References: <20190206181221.27914-1-nicolas.ferre@microchip.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Update the Reset Controller's binding to add new SoC compatibility string. Signed-off-by: Nicolas Ferre Reviewed-by: Rob Herring Acked-by: Alexandre Belloni --- v2: split series and collect tag Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index dd7864f2bb2b..dfc91bc02b97 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -22,6 +22,7 @@ Its subnodes can be: RSTC Reset Controller required properties: - compatible: Should be "atmel,-rstc". can be "at91sam9260", "at91sam9g45", "sama5d3" or "samx7" + it also can be "microchip,sam9x60-rstc" - reg: Should contain registers location and length - clocks: phandle to input clock.