@@ -913,6 +913,16 @@ static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
if (ret)
return ret;
+ if (hba->virt_devs) {
+ struct dev_pm_opp *opp;
+ unsigned long freq = scale_up ? INT_MAX: 0;
+ if (scale_up)
+ opp = dev_pm_opp_find_freq_floor(hba->dev, &freq);
+ else
+ opp = dev_pm_opp_find_freq_ceil(hba->dev, &freq);
+ dev_pm_opp_set_rate(hba->dev, dev_pm_opp_get_freq(opp));
+ }
+
list_for_each_entry(clki, head, list) {
if (!IS_ERR_OR_NULL(clki->clk)) {
if (scale_up && clki->max_freq) {
@@ -1318,6 +1328,7 @@ static int ufshcd_devfreq_init(struct ufs_hba *hba)
struct list_head *clk_list = &hba->clk_list_head;
struct ufs_clk_info *clki;
struct devfreq *devfreq;
+ struct device *virt_dev;
int ret;
/* Skip devfreq if we don't have any clocks in the list */
@@ -1325,8 +1336,14 @@ static int ufshcd_devfreq_init(struct ufs_hba *hba)
return 0;
clki = list_first_entry(clk_list, struct ufs_clk_info, list);
- dev_pm_opp_add(hba->dev, clki->min_freq, 0);
- dev_pm_opp_add(hba->dev, clki->max_freq, 0);
+
+ if (dev_pm_opp_of_add_table(hba->dev)) {
+ dev_pm_opp_add(hba->dev, clki->min_freq, 0);
+ dev_pm_opp_add(hba->dev, clki->max_freq, 0);
+ } else {
+ virt_dev = hba->virt_devs[hba->num_virt_devs -1];
+ dev_pm_opp_set_genpd_virt_dev(hba->dev, virt_dev, 0);
+ }
devfreq = devfreq_add_device(hba->dev,
&ufs_devfreq_profile,
Some platforms like qualcomms sdm845 SoC have a need to set a performance state of a power domain for UFS along with setting the clock rate. Add support for passing this freq/perf state tuple from DT as an OPP table. Modify the driver to read the OPP table and register with OPP layer. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> --- drivers/scsi/ufs/ufshcd.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-)