From patchwork Mon May 27 02:22:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matheus Castello X-Patchwork-Id: 10961995 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30D3A933 for ; Mon, 27 May 2019 02:46:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1FAD028ABA for ; Mon, 27 May 2019 02:46:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 10DA828AC4; Mon, 27 May 2019 02:46:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ABF0428ABA for ; Mon, 27 May 2019 02:46:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726194AbfE0CqS (ORCPT ); Sun, 26 May 2019 22:46:18 -0400 Received: from gateway22.websitewelcome.com ([192.185.47.48]:35364 "EHLO gateway22.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726055AbfE0CqS (ORCPT ); Sun, 26 May 2019 22:46:18 -0400 Received: from cm11.websitewelcome.com (cm11.websitewelcome.com [100.42.49.5]) by gateway22.websitewelcome.com (Postfix) with ESMTP id 5A2F1E93 for ; Sun, 26 May 2019 21:23:17 -0500 (CDT) Received: from br164.hostgator.com.br ([192.185.176.180]) by cmsmtp with SMTP id V5IDhcT0ydnCeV5IDhHjOZ; Sun, 26 May 2019 21:23:17 -0500 X-Authority-Reason: nr=8 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=castello.eng.br; s=default; h=Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To: Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=wcUEqwCmSzTwTOScs99jj/v1rr1UHqi6aLYmirJnCNA=; b=c3cE4r+kv5BtL26BIf7GnVQFcK 8kNVtSVceNHPtN4Hf4vzCRKNOEU3r/xPt58ZvlYEUh4ztGzZkjpLiLPMNXXf14P7u/KkcX7yfxIum oJBEQMDjNv+Cpisfx3z21lM0M2XKJW14IYAkEIperIiQUqxO0ehLY4jAvVrJLTl96XLaGIJ35XgDZ rfUE/s19hh4LmGWN5uit5jB3NEhg5BTXmb7m+iiTIjq4M0MDU7+nAHOwynTo8vTHvSgy23HhGKetY xmVoVYNJhRwqCpTiPEaD/nVST+LVFUfKEv/Uga/Tqc9eTueYoV+RyihuLb4PPKlos4r15bgrgl6h5 yJfSskAA==; Received: from [177.34.20.96] (port=57660 helo=castello.castello.in) by br164.hostgator.com.br with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.91) (envelope-from ) id 1hV5IC-003JNX-Ip; Sun, 26 May 2019 23:23:16 -0300 From: Matheus Castello To: sre@kernel.org, krzk@kernel.org, robh+dt@kernel.org Cc: mark.rutland@arm.com, cw00.choi@samsung.com, b.zolnierkie@samsung.com, lee.jones@linaro.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matheus Castello Subject: [PATCH v3 4/5] power: supply: max17040: Clear ALRT bit when the SOC are above threshold Date: Sun, 26 May 2019 23:22:57 -0300 Message-Id: <20190527022258.32748-5-matheus@castello.eng.br> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190527022258.32748-1-matheus@castello.eng.br> References: <20190527022258.32748-1-matheus@castello.eng.br> MIME-Version: 1.0 X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - br164.hostgator.com.br X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - castello.eng.br X-BWhitelist: no X-Source-IP: 177.34.20.96 X-Source-L: No X-Exim-ID: 1hV5IC-003JNX-Ip X-Source: X-Source-Args: X-Source-Dir: X-Source-Sender: (castello.castello.in) [177.34.20.96]:57660 X-Source-Auth: matheus@castello.eng.br X-Email-Count: 59 X-Source-Cap: Y2FzdGUyNDg7Y2FzdGUyNDg7YnIxNjQuaG9zdGdhdG9yLmNvbS5icg== X-Local-Domain: yes Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In order to not generate duplicate interrupts we clear the ALRT bit when the SOC is in a state that shows that the battery is charged above the set threshold for the SOC low level alert. Signed-off-by: Matheus Castello --- drivers/power/supply/max17040_battery.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.20.1 diff --git a/drivers/power/supply/max17040_battery.c b/drivers/power/supply/max17040_battery.c index 2f4851608cfe..61e6fcfea8a1 100644 --- a/drivers/power/supply/max17040_battery.c +++ b/drivers/power/supply/max17040_battery.c @@ -48,6 +48,7 @@ struct max17040_chip { int status; /* Low alert threshold from 32% to 1% of the State of Charge */ u32 low_soc_alert_threshold; + int alert_bit; }; static int max17040_get_property(struct power_supply *psy, @@ -107,6 +108,7 @@ static void max17040_reset(struct i2c_client *client) static int max17040_set_low_soc_threshold_alert(struct i2c_client *client, u32 level) { + struct max17040_chip *chip = i2c_get_clientdata(client); int ret; u16 data; @@ -118,6 +120,7 @@ static int max17040_set_low_soc_threshold_alert(struct i2c_client *client, data &= MAX17040_ATHD_MASK; data |= level; max17040_write_reg(client, MAX17040_RCOMP, data); + chip->alert_bit = 0; ret = 0; } else { ret = -EINVAL; @@ -144,6 +147,11 @@ static void max17040_get_soc(struct i2c_client *client) soc = max17040_read_reg(client, MAX17040_SOC); chip->soc = (soc >> 8); + + /* check SOC level to clear ALRT bit */ + if (chip->soc > chip->low_soc_alert_threshold && chip->alert_bit) + max17040_set_low_soc_threshold_alert(client, + chip->low_soc_alert_threshold); } static void max17040_get_version(struct i2c_client *client) @@ -229,6 +237,9 @@ static irqreturn_t max17040_thread_handler(int id, void *dev) /* send uevent */ power_supply_changed(chip->battery); + /* ALRT bit is seted */ + chip->alert_bit = 1; + return IRQ_HANDLED; }