diff mbox series

x86/cpu: Add Icelake-NNPI to Intel family

Message ID 20190530123827.8218-1-rajneesh.bhardwaj@linux.intel.com (mailing list archive)
State Not Applicable, archived
Headers show
Series x86/cpu: Add Icelake-NNPI to Intel family | expand

Commit Message

Bhardwaj, Rajneesh May 30, 2019, 12:38 p.m. UTC
Add the CPUID model number of Icelake Neural Network Processor for Deep
Learning Inference (ICL-NNPI) to the Intel family list. Icelake NNPI uses
model number 0x9D and this will be documented in a future version of Intel
Software Development Manual.

Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: platform-driver-x86@vger.kernel.org
Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Len Brown <lenb@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86-ml <x86@kernel.org>
Cc: Linux PM <linux-pm@vger.kernel.org>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
---
 arch/x86/include/asm/intel-family.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Andy Shevchenko June 4, 2019, 4:09 p.m. UTC | #1
On Thu, May 30, 2019 at 06:08:27PM +0530, Rajneesh Bhardwaj wrote:
> Add the CPUID model number of Icelake Neural Network Processor for Deep

I believe we spell "Ice Lake".

> Learning Inference (ICL-NNPI) to the Intel family list. Icelake NNPI uses

Ditto.

> model number 0x9D and this will be documented in a future version of Intel
> Software Development Manual.
> 
> Cc: Borislav Petkov <bp@alien8.de>
> Cc: Dave Hansen <dave.hansen@linux.intel.com>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: "H. Peter Anvin" <hpa@zytor.com>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Kan Liang <kan.liang@linux.intel.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: platform-driver-x86@vger.kernel.org
> Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
> Cc: Len Brown <lenb@kernel.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: x86-ml <x86@kernel.org>
> Cc: Linux PM <linux-pm@vger.kernel.org>
> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
> ---
>  arch/x86/include/asm/intel-family.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
> index 9f15384c504a..087de5d3b93a 100644
> --- a/arch/x86/include/asm/intel-family.h
> +++ b/arch/x86/include/asm/intel-family.h
> @@ -53,6 +53,7 @@
>  #define INTEL_FAM6_CANNONLAKE_MOBILE	0x66
>  
>  #define INTEL_FAM6_ICELAKE_MOBILE	0x7E
> +#define INTEL_FAM6_ICELAKE_NNPI		0x9D
>  
>  /* "Small Core" Processors (Atom) */
>  
> -- 
> 2.17.1
>
Bhardwaj, Rajneesh June 4, 2019, 7:24 p.m. UTC | #2
Hi Andy

On 04-Jun-19 9:39 PM, Andy Shevchenko wrote:
> On Thu, May 30, 2019 at 06:08:27PM +0530, Rajneesh Bhardwaj wrote:
>> Add the CPUID model number of Icelake Neural Network Processor for Deep
> I believe we spell "Ice Lake".

I referred to https://patchwork.kernel.org/patch/10812551/ , 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6e394376ee89233508fa21d006546357f8efee31 
and many others where it mentioned Icelake. I am fine to change it the 
way you are suggesting, please confirm if its still needed and i will 
send a v2.

Thank you.

>
>> Learning Inference (ICL-NNPI) to the Intel family list. Icelake NNPI uses
> Ditto.
>
>> model number 0x9D and this will be documented in a future version of Intel
>> Software Development Manual.
>>
>> Cc: Borislav Petkov <bp@alien8.de>
>> Cc: Dave Hansen <dave.hansen@linux.intel.com>
>> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>> Cc: "H. Peter Anvin" <hpa@zytor.com>
>> Cc: Ingo Molnar <mingo@redhat.com>
>> Cc: Kan Liang <kan.liang@linux.intel.com>
>> Cc: Peter Zijlstra <peterz@infradead.org>
>> Cc: platform-driver-x86@vger.kernel.org
>> Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
>> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
>> Cc: Len Brown <lenb@kernel.org>
>> Cc: Thomas Gleixner <tglx@linutronix.de>
>> Cc: x86-ml <x86@kernel.org>
>> Cc: Linux PM <linux-pm@vger.kernel.org>
>> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
>> ---
>>   arch/x86/include/asm/intel-family.h | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
>> index 9f15384c504a..087de5d3b93a 100644
>> --- a/arch/x86/include/asm/intel-family.h
>> +++ b/arch/x86/include/asm/intel-family.h
>> @@ -53,6 +53,7 @@
>>   #define INTEL_FAM6_CANNONLAKE_MOBILE	0x66
>>   
>>   #define INTEL_FAM6_ICELAKE_MOBILE	0x7E
>> +#define INTEL_FAM6_ICELAKE_NNPI		0x9D
>>   
>>   /* "Small Core" Processors (Atom) */
>>   
>> -- 
>> 2.17.1
>>
Andy Shevchenko June 5, 2019, 10:32 a.m. UTC | #3
On Wed, Jun 05, 2019 at 12:54:12AM +0530, Bhardwaj, Rajneesh wrote:
> Hi Andy
> 
> On 04-Jun-19 9:39 PM, Andy Shevchenko wrote:
> > On Thu, May 30, 2019 at 06:08:27PM +0530, Rajneesh Bhardwaj wrote:
> > > Add the CPUID model number of Icelake Neural Network Processor for Deep
> > I believe we spell "Ice Lake".
> 
> I referred to https://patchwork.kernel.org/patch/10812551/ , https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=6e394376ee89233508fa21d006546357f8efee31
> and many others where it mentioned Icelake. I am fine to change it the way
> you are suggesting, please confirm if its still needed and i will send a v2.

I think the references have a mistake as well.
diff mbox series

Patch

diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h
index 9f15384c504a..087de5d3b93a 100644
--- a/arch/x86/include/asm/intel-family.h
+++ b/arch/x86/include/asm/intel-family.h
@@ -53,6 +53,7 @@ 
 #define INTEL_FAM6_CANNONLAKE_MOBILE	0x66
 
 #define INTEL_FAM6_ICELAKE_MOBILE	0x7E
+#define INTEL_FAM6_ICELAKE_NNPI		0x9D
 
 /* "Small Core" Processors (Atom) */