| Message ID | 20190604173223.4229-2-nsaenzjulienne@suse.de (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | cpufreq support for the Raspberry Pi | expand |
Nicolas Saenz Julienne <nsaenzjulienne@suse.de> writes: > Raspberry Pi's firmware controls this pll, we should use the firmware > interface to access it. > > Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by: Eric Anholt <eric@anholt.net> If someone ever has a non-rpi 2835 to support, they can resurrect this.
Am 04.06.19 um 19:32 schrieb Nicolas Saenz Julienne: > Raspberry Pi's firmware controls this pll, we should use the firmware > interface to access it. > > Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> > --- > drivers/clk/bcm/clk-bcm2835.c | 25 ------------------------- > 1 file changed, 25 deletions(-) > > diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c > index 770bb01f523e..ccb0319fc2e9 100644 > --- a/drivers/clk/bcm/clk-bcm2835.c > +++ b/drivers/clk/bcm/clk-bcm2835.c > @@ -1651,31 +1651,6 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { > .fixed_divider = 1, > .flags = CLK_SET_RATE_PARENT), > > - /* PLLB is used for the ARM's clock. */ How about leaving a short comment, that these clocks are now handled by a different driver?
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 770bb01f523e..ccb0319fc2e9 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1651,31 +1651,6 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), - /* PLLB is used for the ARM's clock. */ - [BCM2835_PLLB] = REGISTER_PLL( - .name = "pllb", - .cm_ctrl_reg = CM_PLLB, - .a2w_ctrl_reg = A2W_PLLB_CTRL, - .frac_reg = A2W_PLLB_FRAC, - .ana_reg_base = A2W_PLLB_ANA0, - .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, - .lock_mask = CM_LOCK_FLOCKB, - - .ana = &bcm2835_ana_default, - - .min_rate = 600000000u, - .max_rate = 3000000000u, - .max_fb_rate = BCM2835_MAX_FB_RATE), - [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( - .name = "pllb_arm", - .source_pll = "pllb", - .cm_reg = CM_PLLB, - .a2w_reg = A2W_PLLB_ARM, - .load_mask = CM_PLLB_LOADARM, - .hold_mask = CM_PLLB_HOLDARM, - .fixed_divider = 1, - .flags = CLK_SET_RATE_PARENT), - /* * PLLC is the core PLL, used to drive the core VPU clock. *
Raspberry Pi's firmware controls this pll, we should use the firmware interface to access it. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> --- drivers/clk/bcm/clk-bcm2835.c | 25 ------------------------- 1 file changed, 25 deletions(-)