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Thu, 25 Jul 2019 14:43:25 +0000 (GMT) From: k.konieczny@partner.samsung.com To: k.konieczny@partner.samsung.com Cc: Marek Szyprowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi , Krzysztof Kozlowski , Kukjin Kim , Kyungmin Park , Mark Rutland , MyungJoo Ham , Nishanth Menon , Rob Herring , Stephen Boyd , Viresh Kumar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v4 3/5] ARM: dts: exynos: add initial data for coupled regulators for Exynos5422/5800 Date: Thu, 25 Jul 2019 16:42:58 +0200 Message-Id: <20190725144300.25014-4-k.konieczny@partner.samsung.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190725144300.25014-1-k.konieczny@partner.samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA01Se0gTcRzvd7fbnavZOYX90tCahBaoGVm/SKTIYEVBQYFUUkvPKeqUnY+y P/KxnFmppOEjsYdJY/jIV8pMSV1uYW6KotIoDLWHzSx8oFiubafUf5/7fl6/DxyFiyyEJxWn SGGUClmChC/gvexbMQVsfX0ocm9hOR81ljUQaGzhC4Ee6U0EKuiyAVQ4+R1HZvMLEg1kW0nU NDlKoGFdJR/N39MDVGbuwlCd/gOJasaGMGTJ0vCRdXkAQ7c69SRaG23koeaJPv4RkbS2qhZI m7S3+dLmZzel3T9eYdKCFi2QGsbbMOl8k/cZ8oIgNJpJiEtjlEFhVwSxxrnTycbQa5WPrWQm GA/MBy4UpPdDjfEJcGARrQFw2XqJwwsAFmk25wOBHc8D+MaSS24YjMslPE70HMBKM8uJ7Ab1 ohpzEHx6F2wp++Y0eNC+sPhjKe4Q4fQKD/brcggH4U7L4XuLyVnNsxss6hmnQUiHw+aSRYxr 84G32zucbS70cfgnqw5wGjf4tnzKecftmpzWh84CSM+ScDLbaA+i7B/hcKTUk8txhzOGlvUF 22F/8V0eh9Ph9JMCkvOqAJxQ/1onDsNewxDhyMHp3bBBF8Sdj8IVXSHg4l3h+Kwb9wRXeP+l Y6PjLIR5uSJOHQCrbO8IDnvBfFv9OpbCtvkasgjsrPhvTMV/Yyr+9T4GuBaImVQ2Uc6w+xRM eiArS2RTFfLAqKTEJmD/5frXDAvtQPf7ag+gKSDZIvTXHooUEbI09npiD4AULvEQtrbbT8Jo 2fUMRpl0WZmawLA9wIviScTCG5smLopouSyFiWeYZEa5wWKUi2cmiPksiw/3p2u1rsW7DGJc 4fcAGxE3o59zPtXV2yhlUWwYvhThPWWtS11KqbfNrQb3nt6WhWLFORk1W6jzwydOVu+YSfA7 FvI05kOl6o7Cfcx8avWc3K87IqTzq++EZnp2VJU3GX/wU0eXyd33wMjdqLO7I6JUB60xz9Vx g4MZ+yU8NlYWvAdXsrK/GhdGv24DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrLIsWRmVeSWpSXmKPExsVy+t/xu7p8ByxjDb78E7HYOGM9q8X1L89Z LeYfOcdq0bfvP6NF/+PXzBbnz29gtzjb9IbdYtPja6wWl3fNYbP43HuE0WLG+X1MFmuP3GW3 WHr9IpPF7cYVbBZvfpxlsmjde4Td4t+1jSwWmx8cY3MQ8lgzbw2jx6ZVnWwem5fUexx8t4fJ o2/LKkaP4ze2M3l83iQXwB6lZ1OUX1qSqpCRX1xiqxRtaGGkZ2hpoWdkYqlnaGwea2VkqqRv Z5OSmpNZllqkb5egl3HivW/BCZuKOQvesDcw3tDrYuTkkBAwkTjxYwpLFyMXh5DAUkaJP5ff MEIkpCUaT69mgrCFJf5c62KDKPrEKHG7eTszSIJNQFViy4yX7CC2iICyxOR705lBipgFOlkl lkz6C5YQFkiVODtrExuIzQLUcLv9FVicV8BFYvOUr1Ab5CU6d+xmAbE5BVwl/jauBbtCCKim sf8YI0S9oMTJmU/AapiB6pu3zmaewCgwC0lqFpLUAkamVYwiqaXFuem5xYZ6xYm5xaV56XrJ +bmbGIFRue3Yz807GC9tDD7EKMDBqMTDe2G5ZawQa2JZcWXuIUYJDmYlEd6tO4BCvCmJlVWp RfnxRaU5qcWHGE2BnpjILCWanA9MGHkl8YamhuYWlobmxubGZhZK4rwdAgdjhATSE0tSs1NT C1KLYPqYODilGhhnaAYYRbPVPE2um95aysIZqDVp8TG5pOxHByzyJNvin0hJL3r8bHf0oefb Z3pk9OjwzLyodNl7VsYebtP5D0MmWR+w2BtoNHVb1VFVtaaiU9u5ba0YN+hL5oZHhxiYiHH9 Oyn5LLk8rcQsS6xnyvEzfKfnfis6IpI0K/HQtYVangsvdb76dEyJpTgj0VCLuag4EQBUdjvH 4AIAAA== X-CMS-MailID: 20190725144326eucas1p29087ad57d52c5978525bcfb050d1a0e6 X-Msg-Generator: CA X-RootMTR: 20190725144326eucas1p29087ad57d52c5978525bcfb050d1a0e6 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190725144326eucas1p29087ad57d52c5978525bcfb050d1a0e6 References: <20190725144300.25014-1-k.konieczny@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Marek Szyprowski Declare Exynos5422/5800 voltage ranges for opp points for big cpu core and bus wcore and couple their voltage supllies as vdd_arm and vdd_int should be in 300mV range. Signed-off-by: Marek Szyprowski [k.konieczny: add missing patch description] Signed-off-by: Kamil Konieczny Reviewed-by: Chanwoo Choi --- arch/arm/boot/dts/exynos5420.dtsi | 34 +++++++++---------- arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 +++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 +++ arch/arm/boot/dts/exynos5800.dtsi | 32 ++++++++--------- 4 files changed, 41 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 5fb2326875dc..0cbf74750553 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -48,62 +48,62 @@ opp-shared; opp-1800000000 { opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1250000>; + opp-microvolt = <1250000 1250000 1500000>; clock-latency-ns = <140000>; }; opp-1700000000 { opp-hz = /bits/ 64 <1700000000>; - opp-microvolt = <1212500>; + opp-microvolt = <1212500 1212500 1500000>; clock-latency-ns = <140000>; }; opp-1600000000 { opp-hz = /bits/ 64 <1600000000>; - opp-microvolt = <1175000>; + opp-microvolt = <1175000 1175000 1500000>; clock-latency-ns = <140000>; }; opp-1500000000 { opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <1137500>; + opp-microvolt = <1137500 1137500 1500000>; clock-latency-ns = <140000>; }; opp-1400000000 { opp-hz = /bits/ 64 <1400000000>; - opp-microvolt = <1112500>; + opp-microvolt = <1112500 1112500 1500000>; clock-latency-ns = <140000>; }; opp-1300000000 { opp-hz = /bits/ 64 <1300000000>; - opp-microvolt = <1062500>; + opp-microvolt = <1062500 1062500 1500000>; clock-latency-ns = <140000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1037500>; + opp-microvolt = <1037500 1037500 1500000>; clock-latency-ns = <140000>; }; opp-1100000000 { opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <1012500>; + opp-microvolt = <1012500 1012500 1500000>; clock-latency-ns = <140000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = < 987500>; + opp-microvolt = < 987500 987500 1500000>; clock-latency-ns = <140000>; }; opp-900000000 { opp-hz = /bits/ 64 <900000000>; - opp-microvolt = < 962500>; + opp-microvolt = < 962500 962500 1500000>; clock-latency-ns = <140000>; }; opp-800000000 { opp-hz = /bits/ 64 <800000000>; - opp-microvolt = < 937500>; + opp-microvolt = < 937500 937500 1500000>; clock-latency-ns = <140000>; }; opp-700000000 { opp-hz = /bits/ 64 <700000000>; - opp-microvolt = < 912500>; + opp-microvolt = < 912500 912500 1500000>; clock-latency-ns = <140000>; }; }; @@ -1100,23 +1100,23 @@ opp00 { opp-hz = /bits/ 64 <84000000>; - opp-microvolt = <925000>; + opp-microvolt = <925000 925000 1400000>; }; opp01 { opp-hz = /bits/ 64 <111000000>; - opp-microvolt = <950000>; + opp-microvolt = <950000 950000 1400000>; }; opp02 { opp-hz = /bits/ 64 <222000000>; - opp-microvolt = <950000>; + opp-microvolt = <950000 950000 1400000>; }; opp03 { opp-hz = /bits/ 64 <333000000>; - opp-microvolt = <950000>; + opp-microvolt = <950000 950000 1400000>; }; opp04 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <987500>; + opp-microvolt = <987500 987500 1400000>; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 25d95de15c9b..65d094256b54 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -428,6 +428,8 @@ regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&buck3_reg>; + regulator-coupled-max-spread = <300000>; }; buck3_reg: BUCK3 { @@ -436,6 +438,8 @@ regulator-max-microvolt = <1400000>; regulator-always-on; regulator-boot-on; + regulator-coupled-with = <&buck2_reg>; + regulator-coupled-max-spread = <300000>; }; buck4_reg: BUCK4 { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index e0f470fe54c8..5c1e965ed7e9 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -257,6 +257,8 @@ regulator-always-on; regulator-boot-on; regulator-ramp-delay = <12500>; + regulator-coupled-with = <&buck3_reg>; + regulator-coupled-max-spread = <300000>; regulator-state-mem { regulator-off-in-suspend; }; @@ -269,6 +271,8 @@ regulator-always-on; regulator-boot-on; regulator-ramp-delay = <12500>; + regulator-coupled-with = <&buck2_reg>; + regulator-coupled-max-spread = <300000>; regulator-state-mem { regulator-off-in-suspend; }; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index 57d3b319fd65..2a74735d161c 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -22,61 +22,61 @@ &cluster_a15_opp_table { opp-1700000000 { - opp-microvolt = <1250000>; + opp-microvolt = <1250000 1250000 1500000>; }; opp-1600000000 { - opp-microvolt = <1250000>; + opp-microvolt = <1250000 1250000 1500000>; }; opp-1500000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1100000 1100000 1500000>; }; opp-1400000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1100000 1100000 1500000>; }; opp-1300000000 { - opp-microvolt = <1100000>; + opp-microvolt = <1100000 1100000 1500000>; }; opp-1200000000 { - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1500000>; }; opp-1100000000 { - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1500000>; }; opp-1000000000 { - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1500000>; }; opp-900000000 { - opp-microvolt = <1000000>; + opp-microvolt = <1000000 1000000 1500000>; }; opp-800000000 { - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; }; opp-700000000 { - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; }; opp-600000000 { opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; clock-latency-ns = <140000>; }; opp-500000000 { opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; clock-latency-ns = <140000>; }; opp-400000000 { opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; clock-latency-ns = <140000>; }; opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; clock-latency-ns = <140000>; }; opp-200000000 { opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <900000>; + opp-microvolt = <900000 900000 1500000>; clock-latency-ns = <140000>; }; };