| Message ID | 20191002060455.3834-4-l.luba@partner.samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Exynos5 DMC interrupt mode | expand |
On Wed, Oct 02, 2019 at 08:04:54AM +0200, Lukasz Luba wrote: > There is a need to access registers at address offset near 0x10000. > These registers are private DMC performance counters, which might be used > as interrupt trigger when overflow. Potential usage is to skip polling > in devfreq framework and switch to interrupt managed bandwidth control. > > Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> > --- > arch/arm/boot/dts/exynos5420.dtsi | 2 +- Thanks, applied but re-ordered with previous one. Applying first interrupts enables the interrupt mode which does not make sense without extended mapping Best regards, Krzysztof
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 98f6c71f57d8..c829bbdc5711 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -239,7 +239,7 @@ dmc: memory-controller@10c20000 { compatible = "samsung,exynos5422-dmc"; - reg = <0x10c20000 0x100>, <0x10c30000 0x100>; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; interrupt-parent = <&combiner>; interrupts = <16 0>, <16 1>; interrupt-names = "drex_0", "drex_1";
There is a need to access registers at address offset near 0x10000. These registers are private DMC performance counters, which might be used as interrupt trigger when overflow. Potential usage is to skip polling in devfreq framework and switch to interrupt managed bandwidth control. Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)