From patchwork Tue Oct 15 21:16:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11191709 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 19CAC15AB for ; Tue, 15 Oct 2019 21:18:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ED7D320663 for ; Tue, 15 Oct 2019 21:18:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PEmBmziv" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389552AbfJOVRN (ORCPT ); Tue, 15 Oct 2019 17:17:13 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:45341 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2389488AbfJOVRM (ORCPT ); Tue, 15 Oct 2019 17:17:12 -0400 Received: by mail-lj1-f196.google.com with SMTP id q64so21730191ljb.12; Tue, 15 Oct 2019 14:17:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vbmgm7OZfiZxyZLfjm0hUKkhnp/cuwLR/94MZqB3XDg=; b=PEmBmzivr4vdO1ukmj7/9imiP/go62le6oa2wkWDLPNe8Sm4maosdmMPGb60KJP6jn hShlZ+7Wf3cs8YTDJGAR3J2wt40o9e4co/rF+rqI/GfcsaSf6T2gAyQZw/9yIpXo8NG9 Dz7FgzoqM48w32jM2i7KXjB3+qEpBC68RMBb+QuJNgy3PNLimV5XmG3JsHf7TDF3tgPd Y3IqbypFypW8wGXL+JuV3Z3dslpUGtcpGZuRsuA772cZ7wtnD+zkXvRy7XnAEJwIDR/E BE3hXBEWbwzCSi5Y7eMXbYG6m1OyBzRkv+HbAk+T/+7j4kv0Vax1f3Ogjvqxu+O6WuB3 7C3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vbmgm7OZfiZxyZLfjm0hUKkhnp/cuwLR/94MZqB3XDg=; b=kXtqNSb+CHLLyqYjsrmRBPzT77qnkWtXsDvVRb936z50Ag7IjZn4HwmFf3qD2u9RWS Y55fWtssojvijPVJhESLs2ffFFTOzTysuIUHR6nnnUGn+e5mMQInssqn4iNBdSK72iXY HpeSFGJJw5KXB1GEjDBfbyHvdnUm3C5vDiQbkvRMAvYx6clz4ENpPCALj+x05BgQ5Y/6 JvfEpwTVlZc8knvhrR/y5/tp73YaoB2EhM618w/YSmqeh/Q7Zulthtqpqis5tvQr3oyY mk31CRGVYsVZ5nXIlDri6n1nUJZNCYTnenqbtE4Jc5wX2CKznW3FLY1zZ3kWJ8t5hrET HhnA== X-Gm-Message-State: APjAAAUms4b5hN0UxUzAa4zPF4w+3KWMXgAaoqP3D8qYA6e3nNTo8eP+ hCAIJrK1yq1VXyq5o78TwXU= X-Google-Smtp-Source: APXvYqw8584qilRFbOi6yNHhZld6QF0W4drtX9MgIzFCJqKwcA+HbwfdRVd/rYdMN/APQZawf0StWg== X-Received: by 2002:a05:651c:113b:: with SMTP id e27mr22947516ljo.125.1571174229197; Tue, 15 Oct 2019 14:17:09 -0700 (PDT) Received: from localhost.localdomain ([94.29.10.250]) by smtp.gmail.com with ESMTPSA id t16sm5269186ljj.29.2019.10.15.14.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 14:17:08 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Michael Turquette , Stephen Boyd Cc: Peter Geis , Nicolas Chauvet , Marcel Ziswiler , linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 09/17] ARM: dts: tegra20: Add CPU clock Date: Wed, 16 Oct 2019 00:16:10 +0300 Message-Id: <20191015211618.20758-10-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191015211618.20758-1-digetx@gmail.com> References: <20191015211618.20758-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org All CPU cores share the same CPU clock. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 8c942e60703e..9c58e7fcf5c0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -851,12 +851,14 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; }; };