From patchwork Thu Oct 24 22:14:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 11210953 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C583514ED for ; Thu, 24 Oct 2019 22:18:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A48EC21BE5 for ; Thu, 24 Oct 2019 22:18:35 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZX3EDQ43" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730663AbfJXWRt (ORCPT ); Thu, 24 Oct 2019 18:17:49 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:42653 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730619AbfJXWRs (ORCPT ); Thu, 24 Oct 2019 18:17:48 -0400 Received: by mail-lf1-f68.google.com with SMTP id z12so20399640lfj.9; Thu, 24 Oct 2019 15:17:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vbmgm7OZfiZxyZLfjm0hUKkhnp/cuwLR/94MZqB3XDg=; b=ZX3EDQ43NdUTVE1tNK2y3ebaWotwJnWbopHcCIFVD/ODkoQstIaIicjjXB5IYWlHMS U4+S7Laaw4fx/P+EjcLhPE9+8Y04Ku3kssNRJRa3STxqlAYPvFB4Jh0PT68O8Sz1QzBe RDBZTzCDPI/Bn02MrdnVXgGekDbJGr0re4DFMEeFWDcYxyqF9dZ2KnaVpxMY8LfSSL7n WqSc7Pi3/vgkYh9U6LYjxRjxuxmQlDNhe4UmmWyFgidH4DJVtHFpaTsB9OFLlgy26uka vqbNHLRublEXQZtRfnxEtVlzjy8K8T8KOPYyiM3ecGvkjPvZ0n8XvnANsSsBWtIrCGff ed2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vbmgm7OZfiZxyZLfjm0hUKkhnp/cuwLR/94MZqB3XDg=; b=DhCV6HxK/iNTTAVNq5sSyHAmD5aB5uX0tr+P1TAkiSrjrCQlSM/EH/bg4USO1oZM3k 7enyWPeHSgFDZOshcwuTjfuQzuMqCnDfAK+kE05SL0srLL803UWWqcONrx8KdBY6iKLg Lbp96Qs0/0s6ncNHFE7B3Vl5mfgciolGF0726DFrObZb5iiaSPETXrNLYSLXKJKzJlgu 7m3yNzxXaKDlPhiYiMi3DjobFpOS3Tfyl7t0cNKE8DWwXTy/acV9Pm9oTmz+xp6dI8uJ ekqLkuXvGFSyA6fFWTjJWJqA5B5lHevae7/VjMCzBpXLuHFkd6mvYyNQjq/anoAe0kEF ReUw== X-Gm-Message-State: APjAAAWFTpzqu3WJkm+ePXWnlFrzrwWQA3lx7NiNXhEOe2pOm7Z/ZZTF J9hn5N8qYJTtP6hZpsJpivo= X-Google-Smtp-Source: APXvYqzJKPdBZJcOVWa98+Zhk/pQ9KxUWUH8Fzyupz8ciu9eqmO1DU1xYNPfB+ofyxp6068gq6QbdQ== X-Received: by 2002:ac2:41d4:: with SMTP id d20mr310746lfi.24.1571955465856; Thu, 24 Oct 2019 15:17:45 -0700 (PDT) Received: from localhost.localdomain (94-29-10-250.dynamic.spd-mgts.ru. [94.29.10.250]) by smtp.gmail.com with ESMTPSA id i6sm11338765lfo.83.2019.10.24.15.17.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Oct 2019 15:17:45 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 09/17] ARM: dts: tegra20: Add CPU clock Date: Fri, 25 Oct 2019 01:14:08 +0300 Message-Id: <20191024221416.14197-10-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191024221416.14197-1-digetx@gmail.com> References: <20191024221416.14197-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org All CPU cores share the same CPU clock. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 8c942e60703e..9c58e7fcf5c0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -851,12 +851,14 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; }; };