Message ID | 20191029220019.26773-14-digetx@gmail.com (mailing list archive) |
---|---|
State | Not Applicable, archived |
Headers | show |
Series | More improvements for Tegra30 devfreq driver | expand |
On Wed, Oct 30, 2019 at 01:00:13AM +0300, Dmitry Osipenko wrote: > Increase sampling period by 4ms to get a nicer pow2 value, converting > diving into shifts in the code. That's more preferable for Tegra30 that > doesn't have hardware divider instructions because of older Cortex-A9 CPU. > In a result boosting events are delayed by 4ms, which is not sensible in > practice at all. This is made irrelevant by patch 17. Best Regards, Michał Mirosław
diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c index 9da62f695859..9cbee82880ff 100644 --- a/drivers/devfreq/tegra30-devfreq.c +++ b/drivers/devfreq/tegra30-devfreq.c @@ -67,7 +67,7 @@ * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128 */ #define ACTMON_AVERAGE_WINDOW_LOG2 6 -#define ACTMON_SAMPLING_PERIOD 12 /* ms */ +#define ACTMON_SAMPLING_PERIOD 16 /* ms */ #define ACTMON_DEFAULT_AVG_BAND 6 /* 1/10 of % */ #define KHZ 1000