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[94.29.10.250]) by smtp.gmail.com with ESMTPSA id c24sm553812lfm.20.2019.10.30.14.35.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2019 14:35:26 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 03/10] clk: tegra: cclk: Add helpers for handling PLLX rate changes Date: Thu, 31 Oct 2019 00:33:53 +0300 Message-Id: <20191030213400.29434-4-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191030213400.29434-1-digetx@gmail.com> References: <20191030213400.29434-1-digetx@gmail.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org CCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra-super-cclk.c | 34 ++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 36 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c index 5cff8363c978..c7e4be0efc59 100644 --- a/drivers/clk/tegra/clk-tegra-super-cclk.c +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c @@ -25,6 +25,9 @@ #define SUPER_CDIV_ENB BIT(31) +static struct tegra_clk_super_mux *cclk_super; +static bool cclk_on_pllx; + static u8 cclk_super_get_parent(struct clk_hw *hw) { return tegra_clk_super_ops.get_parent(hw); @@ -115,6 +118,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name, struct clk_init_data init; u32 val; + if (WARN_ON(cclk_super)) + return ERR_PTR(-EBUSY); + super = kzalloc(sizeof(*super), GFP_KERNEL); if (!super) return ERR_PTR(-ENOMEM); @@ -171,6 +177,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name, clk = clk_register(NULL, &super->hw); if (IS_ERR(clk)) kfree(super); + else + cclk_super = super; return clk; } + +int tegra_cclk_pre_pllx_rate_change(void) +{ + if (IS_ERR_OR_NULL(cclk_super)) + return -EINVAL; + + if (cclk_super_get_parent(&cclk_super->hw) == PLLX_INDEX) + cclk_on_pllx = true; + else + cclk_on_pllx = false; + + /* + * CPU needs to be temporarily re-parented away from PLLX if PLLX + * changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs. + */ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLP_INDEX); + + return 0; +} + +void tegra_cclk_post_pllx_rate_change(void) +{ + if (cclk_on_pllx) + cclk_super_set_parent(&cclk_super->hw, PLLX_INDEX); +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index fa18bef914af..0afe28f4372b 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -771,6 +771,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +int tegra_cclk_pre_pllx_rate_change(void); +void tegra_cclk_post_pllx_rate_change(void); /** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC