From patchwork Mon May 18 09:24:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Lu X-Patchwork-Id: 11555063 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22CBC14C0 for ; Mon, 18 May 2020 09:25:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0652920801 for ; Mon, 18 May 2020 09:25:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="tpTvXBQi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726490AbgERJYy (ORCPT ); Mon, 18 May 2020 05:24:54 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:12679 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726040AbgERJYy (ORCPT ); Mon, 18 May 2020 05:24:54 -0400 X-UUID: 96be21da88fd42a9b664bb8f49c26be1-20200518 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=xOZ4MeTRfS9iV1mfQHvql2zLgBjMD0iQhXwC9YzCwxc=; b=tpTvXBQirvN7i/oouboCalTvovnhTaIagoshnPCqqT5a8shY4howIT6LF/hJjLPLOBH+drWfFIZBMahlMxO1bOxdNXfYGhot3jRuPSAu7PEd9xks5so2Oi92kMbRDEOs/25NTexTIJ07YZv5GTX5eLTD8th6+5ONxtcPwSVl8/U=; X-UUID: 96be21da88fd42a9b664bb8f49c26be1-20200518 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 668778878; Mon, 18 May 2020 17:24:48 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 18 May 2020 17:24:47 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 18 May 2020 17:24:46 +0800 From: Roger Lu To: Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Matthias Brugger , Nishanth Menon , Roger Lu , , , , , Subject: [PATCH v8 1/3] dt-bindings: power: avs: add mtk svs dt-bindings Date: Mon, 18 May 2020 17:24:02 +0800 Message-ID: <20200518092403.22647-2-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200518092403.22647-1-roger.lu@mediatek.com> References: <20200518092403.22647-1-roger.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Document the binding for enabling mtk svs on MediaTek SoC. Signed-off-by: Roger Lu --- .../bindings/power/avs/mtk_svs.yaml | 141 ++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/avs/mtk_svs.yaml diff --git a/Documentation/devicetree/bindings/power/avs/mtk_svs.yaml b/Documentation/devicetree/bindings/power/avs/mtk_svs.yaml new file mode 100644 index 000000000000..77ab606814ce --- /dev/null +++ b/Documentation/devicetree/bindings/power/avs/mtk_svs.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/avs/mtk_svs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Introduce SVS engine + +maintainers: + - Kevin Hilman + - Nishanth Menon + +description: |+ + The SVS (Smart Voltage Scaling) engine is a piece of hardware which is + used to calculate optimized voltage values of several power domains, + e.g. CPU/GPU/CCI, according to chip process corner, temperatures, + and other factors. Then DVFS driver could apply those optimized voltage + values to reduce power consumption. + +properties: + compatible: + const: mediatek,mt8183-svs + + reg: + description: Address range of the MTK SVS controller. + maxItems: 1 + + interrupts: + description: IRQ for the MTK SVS controller. + maxItems: 1 + + clocks: + description: Main clock for svs controller to work. + + clock-names: + const: main + + nvmem-cells: + maxItems: 2 + description: + Phandle to the calibration data provided by a nvmem device. + + nvmem-cell-names: + items: + - const: svs-calibration-data + - const: calibration-data + +patternProperties: + "^svs-(cpu-little|cpu-big|cci|gpu)$": + type: object + description: + Each subnode represents one SVS bank. + - svs-cpu-little (SVS bank device node of little CPU) + - svs-cpu-big (SVS bank device node of big CPU) + - svs-cci (SVS bank device node of CCI) + - svs-gpu (SVS bank device node of GPU) + + properties: + compatible: + enum: + - mediatek,mt8183-svs-cpu-little + - mediatek,mt8183-svs-cpu-big + - mediatek,mt8183-svs-cci + - mediatek,mt8183-svs-gpu + + power-domains: + description: Phandle to the associated power domain + maxItems: 1 + + operating-points-v2: true + + vcpu-little-supply: + description: PMIC buck of little CPU + + vcpu-big-supply: + description: PMIC buck of big CPU + + vcci-supply: + description: PMIC buck of CCI + + vgpu-spply: + description: PMIC buck of GPU + + required: + - compatible + - operating-points-v2 + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + svs: svs@1100b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", "calibration-data"; + + svs_cpu_little: svs-cpu-little { + compatible = "mediatek,mt8183-svs-cpu-little"; + operating-points-v2 = <&cluster0_opp>; + vcpu-little-supply = <&mt6358_vproc12_reg>; + }; + + svs_cpu_big: svs-cpu-big { + compatible = "mediatek,mt8183-svs-cpu-big"; + operating-points-v2 = <&cluster1_opp>; + vcpu-big-supply = <&mt6358_vproc11_reg>; + }; + + svs_cci: svs-cci { + compatible = "mediatek,mt8183-svs-cci"; + operating-points-v2 = <&cci_opp>; + vcci-supply = <&mt6358_vproc12_reg>; + }; + + svs_gpu: svs-gpu { + compatible = "mediatek,mt8183-svs-gpu"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>; + operating-points-v2 = <&gpu_opp_table>; + vgpu-spply = <&mt6358_vgpu_reg>; + }; + };