From patchwork Tue Oct 13 10:23:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michael Kao X-Patchwork-Id: 11835301 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1AD3E174A for ; Tue, 13 Oct 2020 10:24:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA56D2080A for ; Tue, 13 Oct 2020 10:24:05 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="V5HvdVYD" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729575AbgJMKYF (ORCPT ); Tue, 13 Oct 2020 06:24:05 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:50282 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729123AbgJMKYE (ORCPT ); Tue, 13 Oct 2020 06:24:04 -0400 X-UUID: d848fabbf87a4677b5bbd929647894c6-20201013 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=qiedL0JxT+BhogXj0HkQMKXH7NoJA144Q5PDLAu55v0=; b=V5HvdVYDIVnMjV1ReyIE25A/9J9z/mxi+7NkB1OuCxOlYph/vMTd8BA2APOe5kX0Ih0y8gWT+YmZQ+1d3evIhFSokidgtfHC5dyaileTKtng/JNX3DUZUcWDjZ0tVNsDhFnuoxrEudYfx9CmJA8i2K2PKavoGNb5uOg1XQJBIcE=; X-UUID: d848fabbf87a4677b5bbd929647894c6-20201013 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1401521386; Tue, 13 Oct 2020 18:24:02 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 13 Oct 2020 18:24:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 13 Oct 2020 18:24:00 +0800 From: Michael Kao To: Zhang Rui , Daniel Lezcano , , CC: Eduardo Valentin , Rob Herring , Mark Rutland , Matthias Brugger , , , , , , Matthias Kaehlcke , Michael Kao Subject: [v5 2/3] arm64: dts: mt8183: Configure CPU cooling Date: Tue, 13 Oct 2020 18:23:57 +0800 Message-ID: <20201013102358.22588-3-michael.kao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201013102358.22588-1-michael.kao@mediatek.com> References: <20201013102358.22588-1-michael.kao@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Matthias Kaehlcke Add two passive trip points at 68°C and 80°C for the CPU temperature. Signed-off-by: Matthias Kaehlcke Signed-off-by: Michael Kao Tested-by: Hsin-Yi Wang --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 56 ++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 1cd093cf33f3..0614f18a1ea2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include "mt8183-pinfunc.h" / { @@ -450,6 +451,61 @@ polling-delay = <500>; thermal-sensors = <&thermal 0>; sustainable-power = <5000>; + + trips { + threshold: trip-point@0 { + temperature = <68000>; + hysteresis = <2000>; + type = "passive"; + }; + + target: trip-point@1 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu2 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu3 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution = <3072>; + }; + map1 { + trip = <&target>; + cooling-device = <&cpu4 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu5 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu6 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu7 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; }; /* The tzts1 ~ tzts6 don't need to polling */