| Message ID | 20201116171159.1735315-6-gregory.clement@bootlin.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Improve reset for ocelot and add support for new platfrom | expand |
diff --git a/arch/mips/boot/dts/mscc/jaguar2.dtsi b/arch/mips/boot/dts/mscc/jaguar2.dtsi index 42b2b0a51ddc..f5f7b81c4044 100644 --- a/arch/mips/boot/dts/mscc/jaguar2.dtsi +++ b/arch/mips/boot/dts/mscc/jaguar2.dtsi @@ -60,6 +60,12 @@ cpu_ctrl: syscon@70000000 { reg = <0x70000000 0x2c>; }; + reset@71010008 { + compatible = "mscc,luton-chip-reset"; + reg = <0x71010008 0x4>; + microchip,reset-switch-core; + }; + intc: interrupt-controller@70000070 { compatible = "mscc,jaguar2-icpu-intr"; reg = <0x70000070 0x94>; diff --git a/arch/mips/boot/dts/mscc/luton.dtsi b/arch/mips/boot/dts/mscc/luton.dtsi index 2a170b84c5a9..4a26c2874386 100644 --- a/arch/mips/boot/dts/mscc/luton.dtsi +++ b/arch/mips/boot/dts/mscc/luton.dtsi @@ -56,6 +56,11 @@ cpu_ctrl: syscon@10000000 { reg = <0x10000000 0x2c>; }; + reset@00070090 { + compatible = "mscc,luton-chip-reset"; + reg = <0x70090 0x4>; + }; + intc: interrupt-controller@10000084 { compatible = "mscc,luton-icpu-intr"; reg = <0x10000084 0x70>;
Allow Luton and Jaguar2 SoC to use reset feature by adding the reset node. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> --- arch/mips/boot/dts/mscc/jaguar2.dtsi | 6 ++++++ arch/mips/boot/dts/mscc/luton.dtsi | 5 +++++ 2 files changed, 11 insertions(+)