From patchwork Fri Feb 5 13:45:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tony Lindgren X-Patchwork-Id: 12071219 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 655E8C433E0 for ; Fri, 5 Feb 2021 22:42:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1740564FEB for ; Fri, 5 Feb 2021 22:42:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229999AbhBEWl4 (ORCPT ); Fri, 5 Feb 2021 17:41:56 -0500 Received: from muru.com ([72.249.23.125]:57620 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230264AbhBENqX (ORCPT ); Fri, 5 Feb 2021 08:46:23 -0500 Received: from hillo.muru.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTP id 281BD80F1; Fri, 5 Feb 2021 13:45:53 +0000 (UTC) From: Tony Lindgren To: Amit Kucheria , Daniel Lezcano , Zhang Rui Cc: Eduardo Valentin , Keerthy , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Adam Ford , Carl Philipp Klemm , "H . Nikolaus Schaller" , Merlijn Wajer , Pavel Machek , Peter Ujfalusi , Sebastian Reichel Subject: [PATCH 1/4] thermal: ti-soc-thermal: Skip pointless register access for dra7 Date: Fri, 5 Feb 2021 15:45:31 +0200 Message-Id: <20210205134534.49200-2-tony@atomide.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210205134534.49200-1-tony@atomide.com> References: <20210205134534.49200-1-tony@atomide.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On dra7, there is no Start of Conversion (SOC) register bit and we have an empty bgap_soc_mask in the configuration for the thermal driver. Let's not do pointless reads and writes with the empty mask. There's also no point waiting for End of Conversion bit (EOCZ) to go high on dra7. We only care about it going down, and are now mostly timing out waiting for EOCZ high while it has already gone down. When we add checking for the timeout errors in a later patch, waiting for EOCZ high would cause bogus time out errors. Cc: Adam Ford Cc: Carl Philipp Klemm Cc: Eduardo Valentin Cc: H. Nikolaus Schaller Cc: Merlijn Wajer Cc: Pavel Machek Cc: Peter Ujfalusi Cc: Sebastian Reichel Signed-off-by: Tony Lindgren --- drivers/thermal/ti-soc-thermal/ti-bandgap.c | 29 +++++++++++---------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/ti-soc-thermal/ti-bandgap.c b/drivers/thermal/ti-soc-thermal/ti-bandgap.c --- a/drivers/thermal/ti-soc-thermal/ti-bandgap.c +++ b/drivers/thermal/ti-soc-thermal/ti-bandgap.c @@ -602,29 +602,30 @@ void *ti_bandgap_get_sensor_data(struct ti_bandgap *bgp, int id) static int ti_bandgap_force_single_read(struct ti_bandgap *bgp, int id) { - u32 counter = 1000; - struct temp_sensor_registers *tsr; + struct temp_sensor_registers *tsr = bgp->conf->sensors[id].registers; + u32 counter; /* Select single conversion mode */ if (TI_BANDGAP_HAS(bgp, MODE_CONFIG)) RMW_BITS(bgp, id, bgap_mode_ctrl, mode_ctrl_mask, 0); - /* Start of Conversion = 1 */ - RMW_BITS(bgp, id, temp_sensor_ctrl, bgap_soc_mask, 1); + /* Set Start of Conversion if available */ + if (tsr->bgap_soc_mask) { + RMW_BITS(bgp, id, temp_sensor_ctrl, bgap_soc_mask, 1); - /* Wait for EOCZ going up */ - tsr = bgp->conf->sensors[id].registers; + /* Wait for EOCZ going up */ + counter = 1000; + while (--counter) { + if (ti_bandgap_readl(bgp, tsr->temp_sensor_ctrl) & + tsr->bgap_eocz_mask) + break; + } - while (--counter) { - if (ti_bandgap_readl(bgp, tsr->temp_sensor_ctrl) & - tsr->bgap_eocz_mask) - break; + /* Clear Start of Conversion if available */ + RMW_BITS(bgp, id, temp_sensor_ctrl, bgap_soc_mask, 0); } - /* Start of Conversion = 0 */ - RMW_BITS(bgp, id, temp_sensor_ctrl, bgap_soc_mask, 0); - - /* Wait for EOCZ going down */ + /* Wait for EOCZ going down, always needed even if no bgap_soc_mask */ counter = 1000; while (--counter) { if (!(ti_bandgap_readl(bgp, tsr->temp_sensor_ctrl) &