diff mbox series

[v10,4/8] drivers: thermal: tsens: Use init_common for msm8960

Message ID 20210217194011.22649-5-ansuelsmth@gmail.com (mailing list archive)
State New
Delegated to: Daniel Lezcano
Headers show
Series Add support for ipq8064 tsens | expand

Commit Message

Ansuel Smith Feb. 17, 2021, 7:40 p.m. UTC
Use init_common and drop custom init for msm8960.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/thermal/qcom/tsens-8960.c | 52 +------------------------------
 1 file changed, 1 insertion(+), 51 deletions(-)

Comments

Thara Gopinath March 18, 2021, 9:15 p.m. UTC | #1
On 2/17/21 2:40 PM, Ansuel Smith wrote:
> Use init_common and drop custom init for msm8960.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>

Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>

Warm Regards
Thara

> --- >   drivers/thermal/qcom/tsens-8960.c | 52 +------------------------------
>   1 file changed, 1 insertion(+), 51 deletions(-)
> 
> diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c
> index 3f4fc1ffe679..86585f439985 100644
> --- a/drivers/thermal/qcom/tsens-8960.c
> +++ b/drivers/thermal/qcom/tsens-8960.c
> @@ -173,56 +173,6 @@ static void disable_8960(struct tsens_priv *priv)
>   	regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
>   }
>   
> -static int init_8960(struct tsens_priv *priv)
> -{
> -	int ret, i;
> -	u32 reg_cntl;
> -
> -	priv->tm_map = dev_get_regmap(priv->dev, NULL);
> -	if (!priv->tm_map)
> -		return -ENODEV;
> -
> -	/*
> -	 * The status registers for each sensor are discontiguous
> -	 * because some SoCs have 5 sensors while others have more
> -	 * but the control registers stay in the same place, i.e
> -	 * directly after the first 5 status registers.
> -	 */
> -	for (i = 0; i < priv->num_sensors; i++) {
> -		if (i >= 5)
> -			priv->sensor[i].status = S0_STATUS_ADDR + 40;
> -		priv->sensor[i].status += i * 4;
> -	}
> -
> -	reg_cntl = SW_RST;
> -	ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
> -	if (ret)
> -		return ret;
> -
> -	if (priv->num_sensors > 1) {
> -		reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
> -		reg_cntl &= ~SW_RST;
> -		ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
> -					 CONFIG_MASK, CONFIG);
> -	} else {
> -		reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16);
> -		reg_cntl &= ~CONFIG_MASK_8660;
> -		reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660;
> -	}
> -
> -	reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
> -	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
> -	if (ret)
> -		return ret;
> -
> -	reg_cntl |= EN;
> -	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
> -	if (ret)
> -		return ret;
> -
> -	return 0;
> -}
> -
>   static int calibrate_8960(struct tsens_priv *priv)
>   {
>   	int i;
> @@ -346,7 +296,7 @@ static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = {
>   };
>   
>   static const struct tsens_ops ops_8960 = {
> -	.init		= init_8960,
> +	.init		= init_common,
>   	.calibrate	= calibrate_8960,
>   	.get_temp	= get_temp_8960,
>   	.enable		= enable_8960,
>
diff mbox series

Patch

diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c
index 3f4fc1ffe679..86585f439985 100644
--- a/drivers/thermal/qcom/tsens-8960.c
+++ b/drivers/thermal/qcom/tsens-8960.c
@@ -173,56 +173,6 @@  static void disable_8960(struct tsens_priv *priv)
 	regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
 }
 
-static int init_8960(struct tsens_priv *priv)
-{
-	int ret, i;
-	u32 reg_cntl;
-
-	priv->tm_map = dev_get_regmap(priv->dev, NULL);
-	if (!priv->tm_map)
-		return -ENODEV;
-
-	/*
-	 * The status registers for each sensor are discontiguous
-	 * because some SoCs have 5 sensors while others have more
-	 * but the control registers stay in the same place, i.e
-	 * directly after the first 5 status registers.
-	 */
-	for (i = 0; i < priv->num_sensors; i++) {
-		if (i >= 5)
-			priv->sensor[i].status = S0_STATUS_ADDR + 40;
-		priv->sensor[i].status += i * 4;
-	}
-
-	reg_cntl = SW_RST;
-	ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl);
-	if (ret)
-		return ret;
-
-	if (priv->num_sensors > 1) {
-		reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18);
-		reg_cntl &= ~SW_RST;
-		ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR,
-					 CONFIG_MASK, CONFIG);
-	} else {
-		reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16);
-		reg_cntl &= ~CONFIG_MASK_8660;
-		reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660;
-	}
-
-	reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT;
-	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
-	if (ret)
-		return ret;
-
-	reg_cntl |= EN;
-	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 static int calibrate_8960(struct tsens_priv *priv)
 {
 	int i;
@@ -346,7 +296,7 @@  static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = {
 };
 
 static const struct tsens_ops ops_8960 = {
-	.init		= init_8960,
+	.init		= init_common,
 	.calibrate	= calibrate_8960,
 	.get_temp	= get_temp_8960,
 	.enable		= enable_8960,