diff mbox series

cpufreq:s5pv210:Fix typo issue

Message ID 20210315130855.9715-1-cxfcosmos@gmail.com (mailing list archive)
State New, archived
Delegated to: viresh kumar
Headers show
Series cpufreq:s5pv210:Fix typo issue | expand

Commit Message

Xiaofeng Cao March 15, 2021, 1:08 p.m. UTC 
change 'freqency' to 'frequency'
change 'accoriding' to 'according'
change 'untile' to 'until'
change 'souce' to 'source'
change 'divier' to 'divider'

Signed-off-by: Xiaofeng Cao <caoxiaofeng@yulong.com>
---
 drivers/cpufreq/s5pv210-cpufreq.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

Comments

Krzysztof Kozlowski March 15, 2021, 1:11 p.m. UTC | #1 
On 15/03/2021 14:08, Xiaofeng Cao wrote:
> change 'freqency' to 'frequency'
> change 'accoriding' to 'according'
> change 'untile' to 'until'
> change 'souce' to 'source'
> change 'divier' to 'divider'
> 
> Signed-off-by: Xiaofeng Cao <caoxiaofeng@yulong.com>
> ---
>  drivers/cpufreq/s5pv210-cpufreq.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 

Thanks, but already fixed here:
https://lore.kernel.org/linux-arm-kernel/20210313034951.13269-1-unixbhaskar@gmail.com/

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/drivers/cpufreq/s5pv210-cpufreq.c b/drivers/cpufreq/s5pv210-cpufreq.c
index 69786e5bbf05..72321c4507af 100644
--- a/drivers/cpufreq/s5pv210-cpufreq.c
+++ b/drivers/cpufreq/s5pv210-cpufreq.c
@@ -91,7 +91,7 @@  static DEFINE_MUTEX(set_freq_lock);
 /* Use 800MHz when entering sleep mode */
 #define SLEEP_FREQ	(800 * 1000)
 
-/* Tracks if cpu freqency can be updated anymore */
+/* Tracks if cpu frequency can be updated anymore */
 static bool no_cpufreq_access;
 
 /*
@@ -190,7 +190,7 @@  static u32 clkdiv_val[5][11] = {
 
 /*
  * This function set DRAM refresh counter
- * accoriding to operating frequency of DRAM
+ * according to operating frequency of DRAM
  * ch: DMC port number 0 or 1
  * freq: Operating frequency of DRAM(KHz)
  */
@@ -378,7 +378,7 @@  static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
 		/*
 		 * 6. Turn on APLL
 		 * 6-1. Set PMS values
-		 * 6-2. Wait untile the PLL is locked
+		 * 6-2. Wait until the PLL is locked
 		 */
 		if (index == L0)
 			writel_relaxed(APLL_VAL_1000, S5P_APLL_CON);
@@ -390,7 +390,7 @@  static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
 		} while (!(reg & (0x1 << 29)));
 
 		/*
-		 * 7. Change souce clock from SCLKMPLL(667Mhz)
+		 * 7. Change source clock from SCLKMPLL(667Mhz)
 		 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
 		 * (667/4=166)->(200/4=50)Mhz
 		 */
@@ -439,7 +439,7 @@  static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
 	}
 
 	/*
-	 * L4 level need to change memory bus speed, hence onedram clock divier
+	 * L4 level need to change memory bus speed, hence onedram clock divider
 	 * and memory refresh parameter should be changed
 	 */
 	if (bus_speed_changing) {