From patchwork Wed Sep 29 04:42:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 12524615 X-Patchwork-Delegate: cw00.choi@samsung.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD731C433FE for ; Wed, 29 Sep 2021 04:43:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9992D6142A for ; Wed, 29 Sep 2021 04:43:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244142AbhI2Eoo (ORCPT ); Wed, 29 Sep 2021 00:44:44 -0400 Received: from new1-smtp.messagingengine.com ([66.111.4.221]:39379 "EHLO new1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244035AbhI2Eol (ORCPT ); Wed, 29 Sep 2021 00:44:41 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.nyi.internal (Postfix) with ESMTP id D5F58580DE0; Wed, 29 Sep 2021 00:43:00 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Wed, 29 Sep 2021 00:43:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=ybub729T/Cjfw ayZ+WJmNLp/2DPQ83BAzIInc4+TvE4=; b=W8pPIrqIVhNmpK4E40XmbuJjRSTQ1 ySTYRxzvbRqQESOCYb/OqKXW1KA485Gx3B6sQzVGdAqENbscgAVPoUSv4G5sjhUw hw1t0ROjZIUK4wEeu6oNx2DVz+zQyJitwcF3LrBTS7UOpkB752QMYhzmiW3Z9JJ7 x6747tiv74yJNqnBJ0w85I0JhmNtwxLPBSOIjEm5E2m20cGZMPW3mw2dqxEZzf8F C1U8Gx2a3lAfbT56aN2XYGFmmle9cTsKn+AMOYBvyznUsatnOFq+xxrLohHt1awN QLWcemMjNgRszap/zl0Ti5JADSqQKvpYm/I7C4beoznJb3Ahwq3amimWw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=ybub729T/CjfwayZ+WJmNLp/2DPQ83BAzIInc4+TvE4=; b=vmx9Dwe2 awcnu/r97QXK12drrX2rkX4/dxUVf6aAQ/a4jYhbGU2eElrCfhhj9L9j2BPXEKef Z298XYO0K+fPqm4bwQj3hGELPQ9r3QyFXYl0bpesHLfnZcbSARulKznXAaWW/CMZ /LJ7t5EavLLMZO8/eSJWj0ScnDIvDRQtZxYa+x+URAWVllpBnfYtNnwG1E/U2F9p NgoFCFY5XDzW3L7vnOHnElsZvx8pwEqP0f2yP1c8fX8UtJSvhpVF7c/t3Uc2dJ2t llc+KZ9PNsA4tzNSPJECzJSHnTYcyTC4Wfdl8oxXSkla6TNIMaJA4hTrf03wo/4/ +ur55IMI7ujrRg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudekuddgkeegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucevlhhushhtvghrufhiiigvpedunecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 29 Sep 2021 00:43:00 -0400 (EDT) From: Samuel Holland To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec , Rob Herring Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH 06/10] dt-bindings: arm: sunxi: Expand MBUS binding Date: Tue, 28 Sep 2021 23:42:50 -0500 Message-Id: <20210929044254.38301-7-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210929044254.38301-1-samuel@sholland.org> References: <20210929044254.38301-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The MBUS provides more than address translation and bandwidth control. It also provides a PMU to measure bandwidth usage by certain masters, and it provides notification via IRQ when they are active or idle. The MBUS is also tightly integrated with the DRAM controller to provide a Memory Dynamic Frequency Scaling (MDFS) feature. In view of this, the MBUS binding needs to represent the hardware resources needed for MDFS, which include the clocks and MMIO range of the adjacent DRAM controller. Add the additional resources for the H3 and A64 compatibles, and a new example showing how they are used. Signed-off-by: Samuel Holland --- .../arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 75 ++++++++++++++++++- 1 file changed, 72 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml index e713a6fe4cf7..c1fb404d2fb3 100644 --- a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml @@ -33,10 +33,33 @@ properties: - allwinner,sun50i-a64-mbus reg: - maxItems: 1 + minItems: 1 + items: + - description: MBUS interconnect/bandwidth/PMU registers + - description: DRAM controller/PHY registers + + reg-names: + items: + - const: "mbus" + - const: "dram" clocks: + minItems: 1 + items: + - description: MBUS interconnect module clock + - description: DRAM controller/PHY module clock + - description: Register bus clock, shared by MBUS and DRAM + + clock-names: + items: + - const: "mbus" + - const: "dram" + - const: "bus" + + interrupts: maxItems: 1 + description: + MBUS PMU activity interrupt. dma-ranges: description: @@ -53,13 +76,42 @@ required: - clocks - dma-ranges +if: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-h3-mbus + - allwinner,sun50i-a64-mbus + +then: + properties: + reg: + minItems: 2 + + clocks: + minItems: 3 + + required: + - reg-names + - clock-names + +else: + properties: + reg: + maxItems: 1 + + clocks: + maxItems: 1 + additionalProperties: false examples: - | - #include + #include + #include - mbus: dram-controller@1c01000 { + dram-controller@1c01000 { compatible = "allwinner,sun5i-a13-mbus"; reg = <0x01c01000 0x1000>; clocks = <&ccu CLK_MBUS>; @@ -69,4 +121,21 @@ examples: #interconnect-cells = <1>; }; + - | + dram-controller@1c62000 { + compatible = "allwinner,sun50i-a64-mbus"; + reg = <0x01c62000 0x1000>, + <0x01c63000 0x1000>; + reg-names = "mbus", "dram"; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + ...