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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 02/21] x86/msr: add AMD CPPC MSR definitions Date: Fri, 29 Oct 2021 21:02:22 +0800 Message-ID: <20211029130241.1984459-3-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 42eb8a05-b429-4fe3-83c4-08d99adc81b6 X-MS-TrafficTypeDiagnostic: BY5PR12MB4965: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1107; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: abd8ChP2Y7yHLrWOL/TpcKnI9zoU1+MPS41+F/ge/TZ39+K3/alYa7UktJzUY3dfhGeOE087zMyK4LztHIpC20JvoM9vLIhr0XGbbXAfGS/UFp0JHw4TkLUbx+xgiTBdZTc8uhoCv8aWT+DH1BlzMwdTvSELn/MbRUBkY7q/I79N5UMoHeO/w+iezJu3JH+8+gSz2G9OkvVlfh7xtv3CY4bCuBrm24iJ8MHeaPGysbb7zFVsHkF4TWrsRJLf4/KIy0oV/mQH0mwA/ouQKfjAqDHa7JpK9j/OpKEhZvFEJziOvx/u3mZfvexLLPic6wQDARHn9FaxzrVJRpBNlwcjXZYTUP3Ydia/GmeKNBgmtjjke20aAfgyn/OCIM9dc4SgCCyOJ4OD4gf3rbN6ba496HpE464ctCzeohNAkGaUgtA4RmmFzAuMV+TcqQ/HzkCgWT1s6m3ZU0zW5MC9tSeitlY5sKBPG6q04q0HD5sPaJJXcLD7U7JoyihQpgb1btbgVGekC1e1pb2NJwFKwCP7MKqB34emqCuzSA9MiTVCvxMFLAEI4jL9tptv/Ln3G8c1Jrc5BWOkjk+198oUiURIaz35nUQKvj0scwN5tBQXbs0HLIGLoGZkbz+SXx+sgbDokmFWORLVMjysOX30mPfkGz4NObigF2kw7sbt6sUk7kE8KCnhGimtnsl7a2l7VWMpMApy2ciS+A7EpN7LtvJPUXOTwP8dlotF8H/vBsab76s= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(2906002)(70586007)(70206006)(54906003)(1076003)(26005)(356005)(4326008)(7416002)(508600001)(336012)(82310400003)(47076005)(316002)(186003)(81166007)(5660300002)(426003)(86362001)(7696005)(8936002)(36756003)(2616005)(8676002)(36860700001)(110136005)(16526019)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:03:30.7631 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 42eb8a05-b429-4fe3-83c4-08d99adc81b6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4965 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org AMD CPPC (Collaborative Processor Performance Control) function uses MSR registers to manage the performance hints. So add the MSR register macro here. Signed-off-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index a7c413432b33..ce42e15cf303 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -486,6 +486,23 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* AMD Collaborative Processor Performance Control MSRs */ +#define MSR_AMD_CPPC_CAP1 0xc00102b0 +#define MSR_AMD_CPPC_ENABLE 0xc00102b1 +#define MSR_AMD_CPPC_CAP2 0xc00102b2 +#define MSR_AMD_CPPC_REQ 0xc00102b3 +#define MSR_AMD_CPPC_STATUS 0xc00102b4 + +#define CAP1_LOWEST_PERF(x) (((x) >> 0) & 0xff) +#define CAP1_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) +#define CAP1_NOMINAL_PERF(x) (((x) >> 16) & 0xff) +#define CAP1_HIGHEST_PERF(x) (((x) >> 24) & 0xff) + +#define REQ_MAX_PERF(x) (((x) & 0xff) << 0) +#define REQ_MIN_PERF(x) (((x) & 0xff) << 8) +#define REQ_DES_PERF(x) (((x) & 0xff) << 16) +#define REQ_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9