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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v3 07/21] cpufreq: amd: add fast switch function for amd-pstate Date: Fri, 29 Oct 2021 21:02:27 +0800 Message-ID: <20211029130241.1984459-8-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029130241.1984459-1-ray.huang@amd.com> References: <20211029130241.1984459-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 617ea4af-10ca-41dc-7ec9-08d99adc8e3e X-MS-TrafficTypeDiagnostic: MWHPR12MB1135: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2803; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0Prm7UN0GTyrPXIVnMWbXPuD5coFBGq5w/tsusNJnNg1eL0w6asxEKbGBLR7ZetbJG4kp1e1AgLDlO0IKe+m5BS6uEujlQmJ5QI3pzncDL+E+ucTe549ffBa3n0aXQ/ujAludZhaipGSZIC/4uF0242PY1rlF/CttzuNSGqs0r0PwDGCbPKKVHhttjj4zr23nedKT5l5q/rIRtZk3+ntOV2IStzkm8QcSs/XE5I+XY0pS0gkF/5N+Ex3u09pgNogEnKRTicn6B6qC+D3wVxdcQXIKNuCWjTWNCq2laH/kSuDYSCz8W0xvXr50K81iDpfi3eG/2vvP5Tl4+qKEwZ5cgFkdmGitb0+bJaM+6hhHIPK5Rflgyhn0dVYG14aMpiy7gsSwysUHYYTjILXs0TPGJ6sLc86iR08LCdcD0Q9RxTFyXsCrt7qbVKg5aiNUL8xh9vSACiQl+RMq/hIEpr44+UkP9pp/6z/dgApHhRKLT0LHRWvr/HvgfJzODygNHGJR7smiXs6LxDM65g4knC9oS++LS/IfheR48pC5bjxa5GoZRbuN0ury6YaupR5tJXSQjt6u0Bw2DYUVFj1EyHvQjzErv5Tzf7vn1tlejzLpHODyn6rX/GjnCuKTUizPyeDuqgjtqq7KAX4znIMm37WcL8hrLty4Ll4NCZc11QQcJrlDeIUh7hfB61MDDSNOT2/M6avzWcadSicxGgEd9XppHTtAtkPPNo6pwI7pp187pY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(7416002)(54906003)(336012)(83380400001)(356005)(508600001)(186003)(47076005)(2906002)(426003)(2616005)(82310400003)(70586007)(16526019)(70206006)(110136005)(8676002)(7696005)(4326008)(8936002)(86362001)(36756003)(26005)(1076003)(36860700001)(316002)(5660300002)(81166007)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2021 13:03:51.8949 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 617ea4af-10ca-41dc-7ec9-08d99adc8e3e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1135 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the fast switch function for amd-pstate on the AMD processors which support the full MSR register control. It's able to decrease the lattency on interrupt context. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index a400861c7fdc..55ff03f85608 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -191,6 +191,41 @@ static int amd_pstate_target(struct cpufreq_policy *policy, return 0; } +static void amd_pstate_adjust_perf(unsigned int cpu, + unsigned long min_perf, + unsigned long target_perf, + unsigned long capacity) +{ + unsigned long amd_max_perf, amd_min_perf, amd_des_perf, + amd_cap_perf, lowest_nonlinear_perf; + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + amd_cap_perf = READ_ONCE(cpudata->highest_perf); + lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + + if (target_perf < capacity) + amd_des_perf = DIV_ROUND_UP(amd_cap_perf * target_perf, + capacity); + + amd_min_perf = READ_ONCE(cpudata->highest_perf); + if (min_perf < capacity) + amd_min_perf = DIV_ROUND_UP(amd_cap_perf * min_perf, capacity); + + if (amd_min_perf < lowest_nonlinear_perf) + amd_min_perf = lowest_nonlinear_perf; + + amd_max_perf = amd_cap_perf; + if (amd_max_perf < amd_min_perf) + amd_max_perf = amd_min_perf; + + amd_des_perf = clamp_t(unsigned long, amd_des_perf, + amd_min_perf, amd_max_perf); + + amd_pstate_update(cpudata, amd_min_perf, amd_des_perf, + amd_max_perf, true); +} + static int amd_get_min_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; @@ -311,6 +346,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; + policy->fast_switch_possible = true; + ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, policy->cpuinfo.min_freq); if (ret < 0) { @@ -360,6 +397,7 @@ static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, .target = amd_pstate_target, + .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate",