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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v5 07/22] cpufreq: amd: add fast switch function for amd-pstate Date: Tue, 30 Nov 2021 20:36:26 +0800 Message-ID: <20211130123641.1449041-8-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211130123641.1449041-1-ray.huang@amd.com> References: <20211130123641.1449041-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1628b16a-ff6f-452a-ca0c-08d9b3fe2f7c X-MS-TrafficTypeDiagnostic: DM5PR12MB1706: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2803; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gL+573lm3TxsYXa70C6MMh1Pb6C/Hnpi1SxarKAvneZiHo7wWiWYVpFghxpvc5nS6WcrWy7eIUPtyXr5wTJHHGJS0mBGmgggRDWrHVo0RAn0FH8aMNAmtMLUORhMA8E5EDrObE2eN8SWx4YgqymNoPcFMa0O46rGXgQZ2Y7sGFyFBX6ArEAeiA3dFdyXpykuKyYIeNJ/zzO3ZLac3qnzCgrotGvfE38m7GA624ajEZgGrE0koVuINocIMkF+4XxXz4AuJ0gXefE8AaLA+oTkcofwIvIJIblpANXgcHDtGYDVW3T7UABZNobRlG0VQqQfltTcXYJL7s9X3mz9D6btAbJ4xnEfvpDx8NnrKcyLSXfX3hY3IViWPcMyOwVNrb6CPZapcXo0+9T1QrLrs60cdwXjFQHWOGCs5JPn8Z5WL+eJ9fAp1Xikatt5yXk0et+NhjQA7Bpmkxn0fIoYq4iCzwhE02Wyp3Y7DLj1oaMhwLFFCmljD5GtyS49Q2T+bwbpcaXmap5KBmQr/9/ezPNNYoXHkxegmjqFVGsjs1oCwRg107iWh6LQuB5TDvNrqeiZ435D+AdzyEF/8uuz4Kwb6mztujCLVq9Lu+VFDNSRTr98aL0Q76lz3u/eRbdB1kLk3hPlISQzgnRmOzmq6WHyhOUrZOsgYUzB6mc0/pHVLbC1FNLBG1Qogom5qaoagVl3Gg36ZTKcKfD3BKkrdnVQNStiR8odzlrguqNkhMknTCAg1nVIi6cOT88oYmVWxxp5ISigzeX/0NUETsn2aCMU9ZIL+2WblW6IRDIswkFRQjU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(7696005)(2616005)(1076003)(8676002)(7416002)(47076005)(86362001)(36756003)(356005)(81166007)(110136005)(186003)(5660300002)(36860700001)(54906003)(82310400004)(336012)(70586007)(83380400001)(70206006)(2906002)(316002)(26005)(6666004)(16526019)(508600001)(8936002)(426003)(4326008)(40460700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2021 12:37:34.5800 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1628b16a-ff6f-452a-ca0c-08d9b3fe2f7c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1706 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the fast switch function for amd-pstate on the AMD processors which support the full MSR register control. It's able to decrease the latency on interrupt context. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 20ffbc30118f..cab266b8bf35 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -177,6 +177,39 @@ static int amd_pstate_target(struct cpufreq_policy *policy, return 0; } +static void amd_pstate_adjust_perf(unsigned int cpu, + unsigned long _min_perf, + unsigned long target_perf, + unsigned long capacity) +{ + unsigned long max_perf, min_perf, des_perf, + cap_perf, lowest_nonlinear_perf; + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + cap_perf = READ_ONCE(cpudata->highest_perf); + lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + + des_perf = cap_perf; + if (target_perf < capacity) + des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity); + + min_perf = READ_ONCE(cpudata->highest_perf); + if (_min_perf < capacity) + min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity); + + if (min_perf < lowest_nonlinear_perf) + min_perf = lowest_nonlinear_perf; + + max_perf = cap_perf; + if (max_perf < min_perf) + max_perf = min_perf; + + des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); + + amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true); +} + static int amd_get_min_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; @@ -293,6 +326,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; + policy->fast_switch_possible = true; + ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], FREQ_QOS_MIN, policy->cpuinfo.min_freq); if (ret < 0) { @@ -341,6 +376,7 @@ static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, .target = amd_pstate_target, + .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate",