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Wysocki" , Viresh Kumar , Shuah Khan , "Borislav Petkov" , Peter Zijlstra , Ingo Molnar , Giovanni Gherdovich , Steven Rostedt , CC: Deepak Sharma , Alex Deucher , Mario Limonciello , Steven Noonan , Nathan Fontenot , Jinzhou Su , Xiaojian Du , , , Huang Rui Subject: [PATCH v6 07/14] cpufreq: amd-pstate: add fast switch function for AMD P-State Date: Mon, 20 Dec 2021 00:35:21 +0800 Message-ID: <20211219163528.1023186-8-ray.huang@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211219163528.1023186-1-ray.huang@amd.com> References: <20211219163528.1023186-1-ray.huang@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e6703db7-2534-42f3-3a55-08d9c30db66f X-MS-TrafficTypeDiagnostic: DM5PR1201MB2475:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2803; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wbTyTToy5W+tztiCBGae1Ir7GB3ehL2UBDBUvsOosepxC0DoVtUADsC31xuvYrOMztOpAJbKhKDp0KoeSy6dNEZ54BEBjxvnrbGal8HBQwcvQ0n0p98PuC7RXU+KCIoZWehqvhL38ULWkEmZgA5mOOYUcHWUIE1c4uZY7SA0BdLqyk4+tugFll4aUNqD9IrcYdYd3wH67QlQCkzaEOErrxzpsywPUZ6jB1/z4SPZdCZwc/Sn1XWLnDkE7RhTRJzmfKadKZxu3SISDc9DYKOIalZvd4zMkY0y4WMM4A+bJzNql8ohPotNOLnDHphz+TVu4GWwWqY42T+G1pdauRfjUzA+aScjCCKHzdcMiceStqcIzpt0TksGGHSYCd/O7faKmcxXV+kOFivVW+BC3X+sZImhM+17ToCoCfn26hGT1LYFL5h+JiWtSiwNFd1Q9T9aUoM7hVQFHJxBnkJuxfd56sxpzRusv3x54M8tdXBgBOe6ajEzg4yhTTqf0L6fIm+wJ6GPUvg56RTbK8QM48v57jTLY0MPODBNjYyKoXnipOTxw4y6h9nTlbH6pL2ZUQ4kw8J5aZN0O5uicApwZQpdDA9fYycRaB2fdqYikdXeuWF1FbbtkE/tawph4d3i4RF6vx5Amc0US8S38IED9GzC7F7MRD6kTQ1uVH5c/Eozyg2S5wdqP3mKt7FLQUnmVe6LTI10zPnLFS+qqHG9TaWcr42dUBcJs5/WtTM7zHhol5z8HJlpfOUTcJLFvwObETcLHbMKVRojKo06xG3tMHFUeaBTZNqhA8mvf7dlrWDP6pg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(47076005)(86362001)(36860700001)(16526019)(70206006)(1076003)(36756003)(82310400004)(2906002)(7696005)(2616005)(186003)(26005)(7416002)(83380400001)(6666004)(508600001)(426003)(54906003)(5660300002)(316002)(8936002)(70586007)(336012)(356005)(81166007)(110136005)(4326008)(8676002)(40460700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Dec 2021 16:36:31.1945 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6703db7-2534-42f3-3a55-08d9c30db66f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB2475 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce the fast switch function for AMD P-State on the AMD processors which support the full MSR register control. It's able to decrease the latency on interrupt context. Signed-off-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 70b69c660192..14e8a566ea17 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -183,6 +183,39 @@ static int amd_pstate_target(struct cpufreq_policy *policy, return 0; } +static void amd_pstate_adjust_perf(unsigned int cpu, + unsigned long _min_perf, + unsigned long target_perf, + unsigned long capacity) +{ + unsigned long max_perf, min_perf, des_perf, + cap_perf, lowest_nonlinear_perf; + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + cap_perf = READ_ONCE(cpudata->highest_perf); + lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); + + des_perf = cap_perf; + if (target_perf < capacity) + des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity); + + min_perf = READ_ONCE(cpudata->highest_perf); + if (_min_perf < capacity) + min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity); + + if (min_perf < lowest_nonlinear_perf) + min_perf = lowest_nonlinear_perf; + + max_perf = cap_perf; + if (max_perf < min_perf) + max_perf = min_perf; + + des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); + + amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true); +} + static int amd_get_min_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; @@ -299,6 +332,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) /* It will be updated by governor */ policy->cur = policy->cpuinfo.min_freq; + policy->fast_switch_possible = true; + /* Initial processor data capability frequencies */ cpudata->max_freq = max_freq; cpudata->min_freq = min_freq; @@ -329,6 +364,7 @@ static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, .target = amd_pstate_target, + .adjust_perf = amd_pstate_adjust_perf, .init = amd_pstate_cpu_init, .exit = amd_pstate_cpu_exit, .name = "amd-pstate",