From patchwork Tue Mar 8 00:09:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 12772786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0EC8C433FE for ; Tue, 8 Mar 2022 00:10:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245572AbiCHALH (ORCPT ); Mon, 7 Mar 2022 19:11:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343988AbiCHALG (ORCPT ); Mon, 7 Mar 2022 19:11:06 -0500 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 324CB3700E for ; Mon, 7 Mar 2022 16:10:09 -0800 (PST) Received: by mail-pf1-x429.google.com with SMTP id s42so3250518pfg.0 for ; Mon, 07 Mar 2022 16:10:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bdGbRBwf/c8dl5XeVJM5/TA/QnzoWJV9eNGluQ9fvK8=; b=lSxy077phA/tCU7DQ5kVP7i2doyZVCtubNQkrfx7PtTm+JZOWKAMZZcx7d2Q4vtLGW wWGDJMEn92nyIl7iLdUjvv3H/uT/nNYT0VnY+f8F0Sb8SggKWoZFpROyEnq2qFGnUkcd HRua1mCDOAvXZ/j5f2FGxGsVI4e0mp75mNKuk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bdGbRBwf/c8dl5XeVJM5/TA/QnzoWJV9eNGluQ9fvK8=; b=j7UfURH8MD14t6hbaTlrdZI34lu4TaR4ocakVDa7R3bitpeKGWZWyBwunuBbLNUMG7 OMFZZLZ6QU2XCR7PtjoN2iArzlagu8Aky2y2vPvUiTEbj+P0Nno/+sTvz2uVvqruX63A J7c7jWFxd+Cu5ogcad9v9KBkIBEY6TdjR8DJxTovlomKsZLuAlxy/q11bDl23h6z4Ux3 TFI5kkgYYXjr7eALtyzAUIbUUeCcqeqJqjDqvOZaZqCS5spsqRbRdZg0hVhY7jTxf4QA gMRwA8Qze6klrhlggEVmPS9kFtmxdHebhI53nlJqYSkVyrpdK6PS19F5wgrcIPXmjh/J Hcuw== X-Gm-Message-State: AOAM530xZ7DrKt8fILjph6YUmRJkCwDUe8BjsKqbe56il4VkipzfEpf+ T0t7UWs3kcUc9pu7Cz/MueBW1IwJW1sZng== X-Google-Smtp-Source: ABdhPJy8sbnJPbb4XSmbVNbjkdofb0kMj5POeTZi+NODF5lnPa+GmraocOu2XgSVp0Xd1Cf2aOu4Zw== X-Received: by 2002:a63:d018:0:b0:374:a3c1:dfed with SMTP id z24-20020a63d018000000b00374a3c1dfedmr12003576pgf.155.1646698208600; Mon, 07 Mar 2022 16:10:08 -0800 (PST) Received: from localhost ([2620:15c:202:201:e551:44dc:2842:57f1]) by smtp.gmail.com with UTF8SMTPSA id lw18-20020a17090b181200b001bf057106ebsm460641pjb.41.2022.03.07.16.10.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Mar 2022 16:10:08 -0800 (PST) From: Brian Norris To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring Cc: Lin Huang , Heiko Stuebner , Derek Basehore , linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Brian Norris , Rob Herring Subject: [PATCH v3 02/15] dt-bindings: devfreq: rk3399_dmc: Deprecate unused/redundant properties Date: Mon, 7 Mar 2022 16:09:32 -0800 Message-Id: <20220307160918.v3.2.I5ba582cd678d34c03d647e5500db8e33b7524d66@changeid> X-Mailer: git-send-email 2.35.1.616.g0bdcbb4464-goog In-Reply-To: <20220308000945.706701-1-briannorris@chromium.org> References: <20220308000945.706701-1-briannorris@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org These DRAM configuration properties are all handled in ARM Trusted Firmware (and have been since the early days of this SoC), and there are no in-tree users of the DMC binding yet. It's better to just defer to firmware instead of maintaining this large list of properties. There's also some confusion about units: many of these are specified in MHz, but the downstream users and driver code are treating them as Hz, I believe. Rather than straighten all that out, I just drop them. Signed-off-by: Brian Norris Reviewed-by: Rob Herring * Add Reviewed-by tags Reviewed-by: Krzysztof Kozlowski --- Changes in v3: * Add Reviewed-by .../bindings/devfreq/rk3399_dmc.yaml | 42 +++++++++---------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml index ddddddc5c6fb..4ca43b76ed51 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml @@ -47,6 +47,7 @@ properties: finishes, a DCF interrupt is triggered. rockchip,ddr3_speed_bin: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: For values, reference include/dt-bindings/clock/rk3399-ddr.h. Selects the @@ -93,6 +94,7 @@ properties: if bus is idle for standby_idle * DFI clock cycles. rockchip,dram_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less @@ -100,6 +102,7 @@ properties: Note: if DLL was bypassed, the odt will also stop working. rockchip,phy_dll_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: | Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency @@ -107,6 +110,7 @@ properties: Note: PHY DLL and PHY ODT are independent. rockchip,auto_pd_dis_freq: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: Defines the auto PD disable frequency in MHz. @@ -120,18 +124,21 @@ properties: disabled. rockchip,ddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side drive strength in ohms. Default value is 40. rockchip,ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the DRAM side ODT strength in ohms. Default value is 120. rockchip,phy_ddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the phy side CA line @@ -139,12 +146,14 @@ properties: Default value is 40. rockchip,phy_ddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 40. rockchip,phy_ddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is DDR3, this parameter defines the PHY side ODT @@ -159,18 +168,21 @@ properties: disabled. rockchip,lpddr3_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side drive strength in ohms. Default value is 34. rockchip,lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT strength in ohms. Default value is 240. rockchip,phy_lpddr3_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side CA line @@ -178,12 +190,14 @@ properties: Default value is 40. rockchip,phy_lpddr3_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 40. rockchip,phy_lpddr3_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When dram type is LPDDR3, this parameter define the phy side odt @@ -198,42 +212,49 @@ properties: disabled. rockchip,lpddr4_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side drive strength in ohms. Default value is 60. rockchip,lpddr4_dq_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on DQS/DQ line strength in ohms. Default value is 40. rockchip,lpddr4_ca_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on CA line strength in ohms. Default value is 40. rockchip,phy_lpddr4_ca_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side CA line (including command address line) drive strength. Default value is 40. rockchip,phy_lpddr4_ck_cs_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side clock line and CS line drive strength. Default value is 80. rockchip,phy_lpddr4_dq_drv: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) drive strength. Default value is 80. rockchip,phy_lpddr4_odt: + deprecated: true $ref: /schemas/types.yaml#/definitions/uint32 description: When the DRAM type is LPDDR4, this parameter defines the PHY side ODT @@ -262,33 +283,12 @@ examples: clock-names = "dmc_clk"; operating-points-v2 = <&dmc_opp_table>; center-supply = <&ppvar_centerlogic>; - rockchip,ddr3_speed_bin = <21>; rockchip,pd_idle = <0x40>; rockchip,sr_idle = <0x2>; rockchip,sr_mc_gate_idle = <0x3>; rockchip,srpd_lite_idle = <0x4>; rockchip,standby_idle = <0x2000>; - rockchip,dram_dll_dis_freq = <300>; - rockchip,phy_dll_dis_freq = <125>; - rockchip,auto_pd_dis_freq = <666>; rockchip,ddr3_odt_dis_freq = <333>; - rockchip,ddr3_drv = <40>; - rockchip,ddr3_odt = <120>; - rockchip,phy_ddr3_ca_drv = <40>; - rockchip,phy_ddr3_dq_drv = <40>; - rockchip,phy_ddr3_odt = <240>; rockchip,lpddr3_odt_dis_freq = <333>; - rockchip,lpddr3_drv = <34>; - rockchip,lpddr3_odt = <240>; - rockchip,phy_lpddr3_ca_drv = <40>; - rockchip,phy_lpddr3_dq_drv = <40>; - rockchip,phy_lpddr3_odt = <240>; rockchip,lpddr4_odt_dis_freq = <333>; - rockchip,lpddr4_drv = <60>; - rockchip,lpddr4_dq_odt = <40>; - rockchip,lpddr4_ca_odt = <40>; - rockchip,phy_lpddr4_ca_drv = <40>; - rockchip,phy_lpddr4_ck_cs_drv = <80>; - rockchip,phy_lpddr4_dq_drv = <80>; - rockchip,phy_lpddr4_odt = <60>; };