@@ -15,3 +15,7 @@ config INTERCONNECT_IMX8MN
config INTERCONNECT_IMX8MQ
tristate "i.MX8MQ interconnect driver"
depends on INTERCONNECT_IMX
+
+config INTERCONNECT_IMX8MP
+ tristate "i.MX8MP interconnect driver"
+ depends on INTERCONNECT_IMX
@@ -2,8 +2,10 @@ imx-interconnect-objs := imx.o
imx8mm-interconnect-objs := imx8mm.o
imx8mq-interconnect-objs := imx8mq.o
imx8mn-interconnect-objs := imx8mn.o
+imx8mp-interconnect-objs := imx8mp.o
obj-$(CONFIG_INTERCONNECT_IMX) += imx-interconnect.o
obj-$(CONFIG_INTERCONNECT_IMX8MM) += imx8mm-interconnect.o
obj-$(CONFIG_INTERCONNECT_IMX8MQ) += imx8mq-interconnect.o
obj-$(CONFIG_INTERCONNECT_IMX8MN) += imx8mn-interconnect.o
+obj-$(CONFIG_INTERCONNECT_IMX8MP) += imx8mp-interconnect.o
new file mode 100644
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Interconnect framework driver for i.MX8MP SoC
+ *
+ * Copyright 2022 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/interconnect/fsl,imx8mp.h>
+
+#include "imx.h"
+
+static const struct imx_icc_node_adj_desc imx8mp_noc_adj = {
+ .bw_mul = 1,
+ .bw_div = 16,
+ .main_noc = true,
+};
+
+static struct imx_icc_noc_setting noc_setting_nodes[] = {
+ [IMX8MP_ICM_MLMIX] = {
+ .reg = 0x180,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICM_DSP] = {
+ .reg = 0x200,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICM_SDMA2PER] = {
+ .reg = 0x280,
+ .prio_level = 0x80000404,
+ },
+ [IMX8MP_ICM_SDMA2BURST] = {
+ .reg = 0x300,
+ .prio_level = 0x80000404,
+ },
+ [IMX8MP_ICM_SDMA3PER] = {
+ .reg = 0x380,
+ .prio_level = 0x80000404,
+ },
+ [IMX8MP_ICM_SDMA3BURST] = {
+ .reg = 0x400,
+ .prio_level = 0x80000404,
+ },
+ [IMX8MP_ICM_EDMA] = {
+ .reg = 0x480,
+ .prio_level = 0x80000404,
+ },
+ [IMX8MP_ICM_GPU3D] = {
+ .reg = 0x500,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICM_GPU2D] = {
+ .reg = 0x580,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICM_HRV] = {
+ .reg = 0x600,
+ .prio_level = 0x80000202,
+ .ext_control = 1,
+ },
+ [IMX8MP_ICM_LCDIF_HDMI] = {
+ .reg = 0x680,
+ .prio_level = 0x80000202,
+ .ext_control = 1,
+ },
+ [IMX8MP_ICM_HDCP] = {
+ .reg = 0x700,
+ .prio_level = 0x80000505,
+ },
+ [IMX8MP_ICM_NOC_PCIE] = {
+ .reg = 0x780,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICM_USB1] = {
+ .reg = 0x800,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICM_USB2] = {
+ .reg = 0x880,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICM_PCIE] = {
+ .reg = 0x900,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICM_LCDIF_RD] = {
+ .reg = 0x980,
+ .prio_level = 0x80000202,
+ .ext_control = 1,
+ },
+ [IMX8MP_ICM_LCDIF_WR] = {
+ .reg = 0xa00,
+ .prio_level = 0x80000202,
+ .ext_control = 1,
+ },
+ [IMX8MP_ICM_ISI0] = {
+ .reg = 0xa80,
+ .prio_level = 0x80000202,
+ .ext_control = 1,
+ },
+ [IMX8MP_ICM_ISI1] = {
+ .reg = 0xb00,
+ .prio_level = 0x80000202,
+ .ext_control = 1,
+ },
+ [IMX8MP_ICM_ISI2] = {
+ .reg = 0xb80,
+ .prio_level = 0x80000202,
+ .ext_control = 1,
+ },
+ [IMX8MP_ICM_ISP0] = {
+ .reg = 0xc00,
+ .prio_level = 0x80000707,
+ },
+ [IMX8MP_ICM_ISP1] = {
+ .reg = 0xc80,
+ .prio_level = 0x80000707,
+ },
+ [IMX8MP_ICM_DWE] = {
+ .reg = 0xd00,
+ .prio_level = 0x80000707,
+ },
+ [IMX8MP_ICM_VPU_G1] = {
+ .reg = 0xd80,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICM_VPU_G2] = {
+ .reg = 0xe00,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICM_VPU_H1] = {
+ .reg = 0xe80,
+ .prio_level = 0x80000303,
+ },
+ [IMX8MP_ICN_MEDIA] = {
+ .ignore = true,
+ },
+ [IMX8MP_ICN_VIDEO] = {
+ .ignore = true,
+ },
+ [IMX8MP_ICN_AUDIO] = {
+ .ignore = true,
+ },
+ [IMX8MP_ICN_HDMI] = {
+ .ignore = true,
+ },
+ [IMX8MP_ICN_GPU] = {
+ .ignore = true,
+ },
+ [IMX8MP_ICN_HSIO] = {
+ .ignore = true,
+ },
+};
+
+/* Describe bus masters, slaves and connections between them */
+static struct imx_icc_node_desc nodes[] = {
+ DEFINE_BUS_INTERCONNECT("NOC", IMX8MP_ICN_NOC, &imx8mp_noc_adj,
+ IMX8MP_ICS_DRAM, IMX8MP_ICN_MAIN),
+
+ DEFINE_BUS_SLAVE("OCRAM", IMX8MP_ICS_OCRAM, NULL),
+ DEFINE_BUS_SLAVE("DRAM", IMX8MP_ICS_DRAM, NULL),
+ DEFINE_BUS_MASTER("A53", IMX8MP_ICM_A53, IMX8MP_ICN_NOC),
+ DEFINE_BUS_MASTER("SUPERMIX", IMX8MP_ICM_SUPERMIX, IMX8MP_ICN_NOC),
+ DEFINE_BUS_MASTER("GIC", IMX8MP_ICM_GIC, IMX8MP_ICN_NOC),
+ DEFINE_BUS_MASTER("MLMIX", IMX8MP_ICM_MLMIX, IMX8MP_ICN_NOC),
+
+ DEFINE_BUS_INTERCONNECT("NOC_AUDIO", IMX8MP_ICN_AUDIO, NULL, IMX8MP_ICN_NOC),
+ DEFINE_BUS_MASTER("DSP", IMX8MP_ICM_DSP, IMX8MP_ICN_AUDIO),
+ DEFINE_BUS_MASTER("SDMA2PER", IMX8MP_ICM_SDMA2PER, IMX8MP_ICN_AUDIO),
+ DEFINE_BUS_MASTER("SDMA2BURST", IMX8MP_ICM_SDMA2BURST, IMX8MP_ICN_AUDIO),
+ DEFINE_BUS_MASTER("SDMA3PER", IMX8MP_ICM_SDMA3PER, IMX8MP_ICN_AUDIO),
+ DEFINE_BUS_MASTER("SDMA3BURST", IMX8MP_ICM_SDMA3BURST, IMX8MP_ICN_AUDIO),
+ DEFINE_BUS_MASTER("EDMA", IMX8MP_ICM_EDMA, IMX8MP_ICN_AUDIO),
+
+ DEFINE_BUS_INTERCONNECT("NOC_GPU", IMX8MP_ICN_GPU, NULL, IMX8MP_ICN_NOC),
+ DEFINE_BUS_MASTER("GPU 2D", IMX8MP_ICM_GPU2D, IMX8MP_ICN_GPU),
+ DEFINE_BUS_MASTER("GPU 3D", IMX8MP_ICM_GPU3D, IMX8MP_ICN_GPU),
+
+ DEFINE_BUS_INTERCONNECT("NOC_HDMI", IMX8MP_ICN_HDMI, NULL, IMX8MP_ICN_NOC),
+ DEFINE_BUS_MASTER("HRV", IMX8MP_ICM_HRV, IMX8MP_ICN_HDMI),
+ DEFINE_BUS_MASTER("LCDIF_HDMI", IMX8MP_ICM_LCDIF_HDMI, IMX8MP_ICN_HDMI),
+ DEFINE_BUS_MASTER("HDCP", IMX8MP_ICM_HDCP, IMX8MP_ICN_HDMI),
+
+ DEFINE_BUS_INTERCONNECT("NOC_HSIO", IMX8MP_ICN_HSIO, NULL, IMX8MP_ICN_NOC),
+ DEFINE_BUS_MASTER("NOC_PCIE", IMX8MP_ICM_NOC_PCIE, IMX8MP_ICN_HSIO),
+ DEFINE_BUS_MASTER("USB1", IMX8MP_ICM_USB1, IMX8MP_ICN_HSIO),
+ DEFINE_BUS_MASTER("USB2", IMX8MP_ICM_USB2, IMX8MP_ICN_HSIO),
+ DEFINE_BUS_MASTER("PCIE", IMX8MP_ICM_PCIE, IMX8MP_ICN_HSIO),
+
+ DEFINE_BUS_INTERCONNECT("NOC_MEDIA", IMX8MP_ICN_MEDIA, NULL, IMX8MP_ICN_NOC),
+ DEFINE_BUS_MASTER("LCDIF_RD", IMX8MP_ICM_LCDIF_RD, IMX8MP_ICN_MEDIA),
+ DEFINE_BUS_MASTER("LCDIF_WR", IMX8MP_ICM_LCDIF_WR, IMX8MP_ICN_MEDIA),
+ DEFINE_BUS_MASTER("ISI0", IMX8MP_ICM_ISI0, IMX8MP_ICN_MEDIA),
+ DEFINE_BUS_MASTER("ISI1", IMX8MP_ICM_ISI1, IMX8MP_ICN_MEDIA),
+ DEFINE_BUS_MASTER("ISI2", IMX8MP_ICM_ISI2, IMX8MP_ICN_MEDIA),
+ DEFINE_BUS_MASTER("ISP0", IMX8MP_ICM_ISP0, IMX8MP_ICN_MEDIA),
+ DEFINE_BUS_MASTER("ISP1", IMX8MP_ICM_ISP1, IMX8MP_ICN_MEDIA),
+ DEFINE_BUS_MASTER("DWE", IMX8MP_ICM_DWE, IMX8MP_ICN_MEDIA),
+
+ DEFINE_BUS_INTERCONNECT("NOC_VIDEO", IMX8MP_ICN_VIDEO, NULL, IMX8MP_ICN_NOC),
+ DEFINE_BUS_MASTER("VPU G1", IMX8MP_ICM_VPU_G1, IMX8MP_ICN_VIDEO),
+ DEFINE_BUS_MASTER("VPU G2", IMX8MP_ICM_VPU_G2, IMX8MP_ICN_VIDEO),
+ DEFINE_BUS_MASTER("VPU H1", IMX8MP_ICM_VPU_H1, IMX8MP_ICN_VIDEO),
+ DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MP_ICN_MAIN, NULL,
+ IMX8MP_ICN_NOC, IMX8MP_ICS_OCRAM),
+};
+
+static int imx8mp_icc_probe(struct platform_device *pdev)
+{
+ return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), noc_setting_nodes);
+}
+
+static int imx8mp_icc_remove(struct platform_device *pdev)
+{
+ return imx_icc_unregister(pdev);
+}
+
+static struct platform_driver imx8mp_icc_driver = {
+ .probe = imx8mp_icc_probe,
+ .remove = imx8mp_icc_remove,
+ .driver = {
+ .name = "imx8mp-interconnect",
+ },
+};
+
+module_platform_driver(imx8mp_icc_driver);
+MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:imx8mp-interconnect");
new file mode 100644
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Interconnect framework driver for i.MX SoC
+ *
+ * Copyright 2022 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H
+#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H
+
+#define IMX8MP_ICN_NOC 0
+#define IMX8MP_ICN_MAIN 1
+#define IMX8MP_ICS_DRAM 2
+#define IMX8MP_ICS_OCRAM 3
+#define IMX8MP_ICM_A53 4
+#define IMX8MP_ICM_SUPERMIX 5
+#define IMX8MP_ICM_GIC 6
+#define IMX8MP_ICM_MLMIX 7
+
+#define IMX8MP_ICN_AUDIO 8
+#define IMX8MP_ICM_DSP 9
+#define IMX8MP_ICM_SDMA2PER 10
+#define IMX8MP_ICM_SDMA2BURST 11
+#define IMX8MP_ICM_SDMA3PER 12
+#define IMX8MP_ICM_SDMA3BURST 13
+#define IMX8MP_ICM_EDMA 14
+
+#define IMX8MP_ICN_GPU 15
+#define IMX8MP_ICM_GPU2D 16
+#define IMX8MP_ICM_GPU3D 17
+
+#define IMX8MP_ICN_HDMI 18
+#define IMX8MP_ICM_HRV 19
+#define IMX8MP_ICM_LCDIF_HDMI 20
+#define IMX8MP_ICM_HDCP 21
+
+#define IMX8MP_ICN_HSIO 22
+#define IMX8MP_ICM_NOC_PCIE 23
+#define IMX8MP_ICM_USB1 24
+#define IMX8MP_ICM_USB2 25
+#define IMX8MP_ICM_PCIE 26
+
+#define IMX8MP_ICN_MEDIA 27
+#define IMX8MP_ICM_LCDIF_RD 28
+#define IMX8MP_ICM_LCDIF_WR 29
+#define IMX8MP_ICM_ISI0 30
+#define IMX8MP_ICM_ISI1 31
+#define IMX8MP_ICM_ISI2 32
+#define IMX8MP_ICM_ISP0 33
+#define IMX8MP_ICM_ISP1 34
+#define IMX8MP_ICM_DWE 35
+
+#define IMX8MP_ICN_VIDEO 36
+#define IMX8MP_ICM_VPU_G1 37
+#define IMX8MP_ICM_VPU_G2 38
+#define IMX8MP_ICM_VPU_H1 39
+
+#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */