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Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui , Wim Van Sebroeck , Guenter Roeck , Sascha Hauer , NXP Linux Team , Abel Vesa , Viorel Suman , Oliver Graute , Liu Ying , Mirela Rabulea , Peng Fan , Ming Qian , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-input@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-pm@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 02/14] dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file Date: Wed, 29 Jun 2022 19:44:02 +0300 Message-Id: <20220629164414.301813-3-viorel.suman@oss.nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220629164414.301813-1-viorel.suman@oss.nxp.com> References: <20220629164414.301813-1-viorel.suman@oss.nxp.com> X-ClientProxiedBy: AM9P195CA0028.EURP195.PROD.OUTLOOK.COM (2603:10a6:20b:21f::33) To VI1PR04MB5005.eurprd04.prod.outlook.com (2603:10a6:803:57::30) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c9f10556-1a7c-45e4-6f2f-08da59eeb6a8 X-MS-TrafficTypeDiagnostic: AM0PR04MB6401:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-LD-Processed: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?iso-8859-1?q?pQJeIdHlB0HG5RBy8sfFMOZ?= =?iso-8859-1?q?+ZAsFcFUR42pninzrZ5+kTQJ8jNVQbynYuDFiuxFDaVkXX0UKQ07LYarHfXm?= =?iso-8859-1?q?dgB4QfXSZD+MsHIgOFKZcGubccaOopTNKQ1WBu//7VAmzRD7b6KCFWFN4p7p?= =?iso-8859-1?q?Ck2q+vp/Rh6gFV2zBDQ3cgdkoy+HNozfv0JXyAKd3dtqmhH6SW+7Bols9tFp?= =?iso-8859-1?q?Ccs/i447Crk/DwheeHzd/hQDCmkdMrYtipp8EBIcIhggWNdimC+LocfkU7o2?= =?iso-8859-1?q?zXPJxwTUQm4H8+hhCdNd774tAeYdEsPX/2gr6uGy3c6Yem2DBDKG93jy/KB6?= =?iso-8859-1?q?W5q2IIToSrpn3sU31TOXd4hMFNRf4ywRklAmoJZXKpl3Ub19pI5HZyF+mM7l?= =?iso-8859-1?q?7torUkf2+9suSw47tpTLksokeiJDCkxOC2Amqf2yoTsK8yKR7HBsBnntwvHA?= =?iso-8859-1?q?IwaEEepK8jrWk68FZ0TisFazr/j12SyX7YjdN2F6WaTv4+8LE2VHhgsGt1lD?= =?iso-8859-1?q?7qNW/Qaba9EippKLa6Si7GIcD8k/LP1kHrAOx/c772YvnbC3UrRqGr/4/R7k?= =?iso-8859-1?q?6tYyJc7h1+moOtnv+ymknRBX3mBXU9zgmWfL+kf+Ej4MCg9U6wSv8GOKBb55?= =?iso-8859-1?q?7zCs5CE8K7v4HKwu0ZycCTqpZxSbXwqAI6Z71Q0CDAZ44ctzls+2pmshbgTV?= =?iso-8859-1?q?Ag3SXJLwA4dwrPfamJkjIhp6vgXXR7xnMPZSR0U8XoN8BusCqmRerBuUFzRX?= =?iso-8859-1?q?fcnzjd+PlbvHgkqBJkZM/95DA2bwhTJ+MFCKAs9gArtylDURa2460G26B15Q?= =?iso-8859-1?q?Ev98s//kzM/e58QkfX3UmSctFlamKqmFGyEI49uPtBIIl8KuloQ59RtNsNH1?= =?iso-8859-1?q?mVnB8OwRBoILLT7vOuuXNOBnzyNm9v8UOq1FgSQ5cSwlU1KNIQNWoHznz3vA?= =?iso-8859-1?q?LoZ0SatEhmHqjxmWV3FRKMHtk2dyMTj/NTa/MURBWVUwY8caDerJ3EV919FN?= =?iso-8859-1?q?C2/0DQ/q2ABmZCYr/eoO7vy/FXOWX9wofncQgcHZtBtnLPJyP77M+NKQx2WJ?= =?iso-8859-1?q?CEdduI2kT8SvHV+A6kolQr7vWLqBUimj8EgqbtFLiUQ1uVO9ro60EuJe438M?= =?iso-8859-1?q?IlPRNIKyN0LIC4k/EJHIqbHEx0nKOxAtcRj9pyNz87HfcWEWGDCWvr/kbjxD?= =?iso-8859-1?q?sqGhgaiutTqoBgP8wNEG9P2yHr1Qnq/Ivr8rixXq14hj8ha31whTp63rWySc?= =?iso-8859-1?q?6Niz2UaCaC72gAdklDn28aLhmTdshMF4sgnyxto+S95L5ozJ2xt5SvzNxwBz?= =?iso-8859-1?q?7dDzYW9RrvG3+rbghtKjQn6uC/+Lx9LBP5/oACh7et0gSNOSZsxwLcvasuHG?= =?iso-8859-1?q?xWAA+x4Q4Uxq5NWS6N8DDo0uF1mX8KYSWO3V2Bu2I4wICVFdvKsJSz42Bg7F?= =?iso-8859-1?q?fseBRTUE6DbqHbwGSfA/AW0JW6M9y2p7/OIc+dknpYC8mpzhtH+Imlk4BhTt?= =?iso-8859-1?q?nDik/0a7WYMIUV0K79fjFi9EsFw3DOxeKm92r/dGoC+CHzKy7I4ulhFyRcwW?= =?iso-8859-1?q?ZXkK3iiiR6Ro6nJtTPcukrsL5dGRfZd6wNgVz1DTFRqomKGbqqH/pOsVRJZa?= =?iso-8859-1?q?leuNgjZYzfQdv5/0d?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c9f10556-1a7c-45e4-6f2f-08da59eeb6a8 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB5005.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2022 16:45:02.9332 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: pov4ZXrgabKsMwwYpV0n/zHhPWMIS7dZNEJSW9OtNBJFNFzJQC8tayA+OhpkYKYvSl6yFvlXYoXfemu1u4fsiA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6401 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Abel Vesa In order to replace the fsl,scu txt file from bindings/arm/freescale, we need to split it between the right subsystems. This patch documents separately the 'iomux/pinctrl' child node of the SCU main node. Signed-off-by: Abel Vesa Signed-off-by: Viorel Suman --- .../bindings/pinctrl/fsl,scu-pinctrl.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml new file mode 100644 index 000000000000..76a2e7b28172 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - Pinctrl bindings based on SCU Message Protocol + +maintainers: + - Dong Aisheng + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + This binding uses the i.MX common pinctrl binding. + (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt) + +allOf: + - $ref: "pinctrl.yaml#" + +properties: + compatible: + enum: + - fsl,imx8qm-iomuxc + - fsl,imx8qxp-iomuxc + - fsl,imx8dxl-iomuxc + +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 3 integers and represents the pin ID, the mux value + and config setting for the pin. The first 2 integers - pin_id and mux_val - are + specified using a PIN_FUNC_ID macro, which can be found in + . The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to the + appropriate i.MX8 Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + 111 0 0x06000020 + 112 0 0x06000020 + >; + }; + };