diff mbox series

[v3,4/5] Documentation: amd-pstate: add driver working mode introduction

Message ID 20221117073541.3350600-5-Perry.Yuan@amd.com (mailing list archive)
State Mainlined, archived
Headers show
Series AMD Pstate driver Urgent Change | expand

Commit Message

Perry Yuan Nov. 17, 2022, 7:35 a.m. UTC
Introduce the `amd_pstate` driver new working mode with
`amd_pstate=passive` added to kernel command line.
If there is no passive mode enabled by user, amd_pstate driver will be
disabled by default for now.

Acked-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
Tested-by: Wyes Karny <wyes.karny@amd.com>
Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
---
 Documentation/admin-guide/pm/amd-pstate.rst | 30 +++++++++------------
 1 file changed, 13 insertions(+), 17 deletions(-)

Comments

Bagas Sanjaya Nov. 17, 2022, 8:58 a.m. UTC | #1
On Thu, Nov 17, 2022 at 03:35:40PM +0800, Perry Yuan wrote:
> Introduce the `amd_pstate` driver new working mode with
> `amd_pstate=passive` added to kernel command line.
> If there is no passive mode enabled by user, amd_pstate driver will be
> disabled by default for now.
>
><snipped>...
> -.. _shared_mem:
> -
> -``shared_mem``
> -Use a module param (shared_mem) to enable related processors manually with
> -**amd_pstate.shared_mem=1**.
> -Due to the performance issue on the processors with `Shared Memory Support
> -<perf_cap_>`_, we disable it presently and will re-enable this by default
> -once we address performance issue with this solution.
> -
> -To check whether the current processor is using `Full MSR Support <perf_cap_>`_
> -or `Shared Memory Support <perf_cap_>`_ : ::
> -
> -  ray@hr-test1:~$ lscpu | grep cppc
> -  Flags:                           fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd cppc arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
> -
> -If the CPU flags have ``cppc``, then this processor supports `Full MSR Support
> -<perf_cap_>`_. Otherwise, it supports `Shared Memory Support <perf_cap_>`_.
> +Passive Mode
> +------------
> +
> +``amd_pstate=passive``
> +
> +It will be enabled if the ``amd_pstate=passive`` is passed to the kernel in the command line.
> +In this mode, ``amd_pstate`` driver software specifies a desired QoS target in the CPPC
> +performance scale as a relative number. This can be expressed as percentage of nominal
> +performance (infrastructure max). Below the nominal sustained performance level,
> +desired performance expresses the average performance level of the processor subject
> +to the Performance Reduction Tolerance register. Above the nominal performance level,
> +processor must provide at least nominal performance requested and go higher if current
> +operating conditions allow.
>  
>  
>  ``cpupower`` tool support for ``amd-pstate``
> 

Why do you replace shared_mem subsection with passive mode section? It
isn't be mentioned in the patch description.
Perry Yuan Nov. 17, 2022, 9:34 a.m. UTC | #2
[AMD Official Use Only - General]



> -----Original Message-----
> From: Bagas Sanjaya <bagasdotme@gmail.com>
> Sent: Thursday, November 17, 2022 4:58 PM
> To: Yuan, Perry <Perry.Yuan@amd.com>
> Cc: rafael.j.wysocki@intel.com; Huang, Ray <Ray.Huang@amd.com>; 
> viresh.kumar@linaro.org; Limonciello, Mario 
> <Mario.Limonciello@amd.com>; Fontenot, Nathan 
> <Nathan.Fontenot@amd.com>; Deucher, Alexander 
> <Alexander.Deucher@amd.com>; Sharma, Deepak <Deepak.Sharma@amd.com>; 
> Huang, Shimmer <Shimmer.Huang@amd.com>; Meng, Li (Jassmine) 
> <Li.Meng@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Karny, Wyes 
> <Wyes.Karny@amd.com>; Shenoy, Gautham Ranjal <gautham.shenoy@amd.com>; 
> Narayan, Ananth <Ananth.Narayan@amd.com>; linux-pm@vger.kernel.org; 
> linux- kernel@vger.kernel.org
> Subject: Re: [PATCH v3 4/5] Documentation: amd-pstate: add driver 
> working mode introduction
> 
> On Thu, Nov 17, 2022 at 03:35:40PM +0800, Perry Yuan wrote:
> > Introduce the `amd_pstate` driver new working mode with 
> > `amd_pstate=passive` added to kernel command line.
> > If there is no passive mode enabled by user, amd_pstate driver will 
> > be disabled by default for now.
> >
> ><snipped>...
> > -.. _shared_mem:
> > -
> > -``shared_mem``
> > -Use a module param (shared_mem) to enable related processors
> manually
> >with  -**amd_pstate.shared_mem=1**.
> > -Due to the performance issue on the processors with `Shared Memory 
> >Support  -<perf_cap_>`_, we disable it presently and will re-enable 
> >this by default  -once we address performance issue with this solution.
> > -
> > -To check whether the current processor is using `Full MSR Support 
> ><perf_cap_>`_  -or `Shared Memory Support <perf_cap_>`_ : ::
> > -
> > -  ray@hr-test1:~$ lscpu | grep cppc
> > -  Flags:                           fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
> mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext 
> fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc 
> cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 
> sse4_1
> sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm 
> cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch 
> osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext 
> perfctr_llc mwaitx cpb cat_l3
> cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 
> smep
> bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni 
> xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total 
> cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd cppc arat npt 
> lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists 
> pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku 
> ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
> > -
> > -If the CPU flags have ``cppc``, then this processor supports `Full 
> >MSR Support  -<perf_cap_>`_. Otherwise, it supports `Shared Memory
> Support <perf_cap_>`_.
> > +Passive Mode
> > +------------
> > +
> > +``amd_pstate=passive``
> > +
> > +It will be enabled if the ``amd_pstate=passive`` is passed to the 
> > +kernel in
> the command line.
> > +In this mode, ``amd_pstate`` driver software specifies a desired 
> > +QoS target in the CPPC performance scale as a relative number. This 
> > +can be expressed as percentage of nominal performance 
> > +(infrastructure max). Below the nominal sustained performance 
> > +level, desired performance expresses the average performance level 
> > +of the processor subject to the Performance Reduction Tolerance 
> > +register. Above the nominal performance level, processor must 
> > +provide at least nominal
> performance requested and go higher if current operating conditions allow.
> >
> >
> >  ``cpupower`` tool support for ``amd-pstate``
> >
> 
> Why do you replace shared_mem subsection with passive mode section? It 
> isn't be mentioned in the patch description.
shared_mem is not needed any more,  if no cppc flag detected for MSR support, pstate driver will use shared memory interface(cppc acpi) to set/get perf values to the low-level firmware.
There are two type CPPC  only in the amd cppc implementation. 
Removing shared_mem  parameter will make it simple to load amd pstate driver now.

Perry. 

> 
> --
> An old man doll... just what I always wanted! - Clara
diff mbox series

Patch

diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst
index 8f3d30c5a0d8..06e23538f79c 100644
--- a/Documentation/admin-guide/pm/amd-pstate.rst
+++ b/Documentation/admin-guide/pm/amd-pstate.rst
@@ -283,23 +283,19 @@  efficiency frequency management method on AMD processors.
 Kernel Module Options for ``amd-pstate``
 =========================================
 
-.. _shared_mem:
-
-``shared_mem``
-Use a module param (shared_mem) to enable related processors manually with
-**amd_pstate.shared_mem=1**.
-Due to the performance issue on the processors with `Shared Memory Support
-<perf_cap_>`_, we disable it presently and will re-enable this by default
-once we address performance issue with this solution.
-
-To check whether the current processor is using `Full MSR Support <perf_cap_>`_
-or `Shared Memory Support <perf_cap_>`_ : ::
-
-  ray@hr-test1:~$ lscpu | grep cppc
-  Flags:                           fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd cppc arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
-
-If the CPU flags have ``cppc``, then this processor supports `Full MSR Support
-<perf_cap_>`_. Otherwise, it supports `Shared Memory Support <perf_cap_>`_.
+Passive Mode
+------------
+
+``amd_pstate=passive``
+
+It will be enabled if the ``amd_pstate=passive`` is passed to the kernel in the command line.
+In this mode, ``amd_pstate`` driver software specifies a desired QoS target in the CPPC
+performance scale as a relative number. This can be expressed as percentage of nominal
+performance (infrastructure max). Below the nominal sustained performance level,
+desired performance expresses the average performance level of the processor subject
+to the Performance Reduction Tolerance register. Above the nominal performance level,
+processor must provide at least nominal performance requested and go higher if current
+operating conditions allow.
 
 
 ``cpupower`` tool support for ``amd-pstate``