From patchwork Thu Dec 1 21:56:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13061847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51262C47090 for ; Thu, 1 Dec 2022 21:57:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231289AbiLAV50 (ORCPT ); Thu, 1 Dec 2022 16:57:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230462AbiLAV5W (ORCPT ); Thu, 1 Dec 2022 16:57:22 -0500 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A3F4C3FEC; Thu, 1 Dec 2022 13:57:19 -0800 (PST) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 5FCD48536E; Thu, 1 Dec 2022 22:57:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1669931837; bh=+PJjyqiVs8B9i3leJCu6frf2HboWjA36RJN8Zq9aGC8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dLB6IefXY4I8MM25wJoV8nKU3sYxF0Az5g9uvja8aoeGuhxNvex6EGt6vHoVGChEb zNzpWMVwSDemwN9ENx1OfaZCJ3b/VjgJTMUSC1NdNd/nXkNo0LXUDbbJMI0um/b4Aw TdfK0GVUPJm0LxSugG66N/BcPGpyhvYsGw3fg786YXGOfLzi4v2cWYlCKHqCF/np+Q rTRNE+OpG0k6okiIntm3OZutZD1qPCkvhL6UQvCIlRFDxxgOjM60hY4jrOE3xRIWhy WSPUNxET1Z5qcGJ1XRPIL8Jn4juvYfLcxMe3SYYqs2ut9Q/Ktx7ZZioL4xcgyt5lQ9 XZdyLfI2YD0bw== From: Marek Vasut To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Peng Fan , Adam Ford , Alice Guo , Amit Kucheria , Daniel Lezcano , Fabio Estevam , Krzysztof Kozlowski , Li Jun , Lucas Stach , Markus Niebel , NXP Linux Team , Pengutronix Kernel Team , "Rafael J . Wysocki" , Richard Cochran , Rob Herring , Sascha Hauer , Shawn Guo , Zhang Rui , devicetree@vger.kernel.org Subject: [PATCH v2 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Date: Thu, 1 Dec 2022 22:56:50 +0100 Message-Id: <20221201215651.152497-4-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221201215651.152497-1-marex@denx.de> References: <20221201215651.152497-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with calibration values in OCOTP. Add the OCOTP calibration values phandle so the TMU driver can perform this programming. The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4. Reviewed-by: Peng Fan Signed-off-by: Marek Vasut --- Cc: Adam Ford Cc: Alice Guo Cc: Amit Kucheria Cc: Daniel Lezcano Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Li Jun Cc: Lucas Stach Cc: Markus Niebel Cc: NXP Linux Team Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Rafael J. Wysocki Cc: Richard Cochran Cc: Rob Herring Cc: Sascha Hauer Cc: Shawn Guo Cc: Zhang Rui Cc: devicetree@vger.kernel.org To: linux-pm@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- V2: Add RB from Peng --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 513c2de0caa15..0cd7fff47c44d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -496,6 +496,8 @@ tmu: tmu@30260000 { compatible = "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 068f599cdf757..5eef9b274edde 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -498,6 +498,8 @@ tmu: tmu@30260000 { compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ddcd5e23ba47d..0173e394ad4d8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -380,6 +380,8 @@ tmu: tmu@30260000 { compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; }; @@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */ eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; }; + + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ + reg = <0x264 0x10>; + }; }; anatop: clock-controller@30360000 {