From patchwork Fri Dec 2 16:23:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 13062892 X-Patchwork-Delegate: daniel.lezcano@linaro.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34E16C636F8 for ; Fri, 2 Dec 2022 16:25:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231470AbiLBQZm (ORCPT ); Fri, 2 Dec 2022 11:25:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233994AbiLBQZX (ORCPT ); Fri, 2 Dec 2022 11:25:23 -0500 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E12B38BD; Fri, 2 Dec 2022 08:24:15 -0800 (PST) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id D916D85023; Fri, 2 Dec 2022 17:24:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1669998253; bh=bC+za2ZVM8M2aK2qyKqPCjL7Y/MV2IrnYhSRg8YnxvE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TY7Dm6p1ZmzQ4WYb8sPsLfvSgGE/+WNHnXx10T5i3o8C/bunCYVKXYX9jt3HnNvUd E3azup13Z2vJAG4JFHcs7Xp4wRZ9avxetH5A00ph3nK+xbRc999broV4MbRWQ7YhXD dZBqWUNkJnNfsIT6OHgIDk9AStHDoc/HmXLDBv/eer0ygYXftMaoW69iPcjnThY24U wTa1M3noMGLKpdcEOHqMWXrDxFuIa8ITEsl85dggCgzthHhA4wJ1xu589XgRWg17nf /fVzaGvchLtKl22JkEF1aqOYhN1aLYJJw/IBFrr3gpA1vOZQBJOjVLXTR4KbQdDgFz n5oeifLX6jR5g== From: Marek Vasut To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Peng Fan , Adam Ford , Alice Guo , Amit Kucheria , Daniel Lezcano , Fabio Estevam , Krzysztof Kozlowski , Li Jun , Lucas Stach , Markus Niebel , NXP Linux Team , Pengutronix Kernel Team , "Rafael J . Wysocki" , Richard Cochran , Rob Herring , Sascha Hauer , Shawn Guo , Zhang Rui , devicetree@vger.kernel.org Subject: [PATCH v3 3/5] arm64: dts: imx8m: Document the fuse address calculation Date: Fri, 2 Dec 2022 17:23:51 +0100 Message-Id: <20221202162353.274009-3-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221202162353.274009-1-marex@denx.de> References: <20221202162353.274009-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The mapping from OCOTP reg DT property to Fusemap Descriptions Table in the datasheet is often unclear. Add a comment to make it easier to find out how it works. No functional change. Reviewed-by: Peng Fan Signed-off-by: Marek Vasut --- Cc: Adam Ford Cc: Alice Guo Cc: Amit Kucheria Cc: Daniel Lezcano Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Li Jun Cc: Lucas Stach Cc: Markus Niebel Cc: NXP Linux Team Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Rafael J. Wysocki Cc: Richard Cochran Cc: Rob Herring Cc: Sascha Hauer Cc: Shawn Guo Cc: Zhang Rui Cc: devicetree@vger.kernel.org To: linux-pm@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- V2: Add RB from Peng V3: No change --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 ++++++++++++++++--- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 ++++++++++++++++--- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 21 +++++++++++++++++---- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 ++++++++++++++++--- 4 files changed, 65 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 423cb36cbcd53..513c2de0caa15 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -563,15 +563,28 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mm_uid: unique-id@4 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 312e3abc35ea8..068f599cdf757 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -564,15 +564,28 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mn_uid: unique-id@4 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c9459ed21b243..ddcd5e23ba47d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -426,19 +426,32 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mp_uid: unique-id@8 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x8 0x8> describes fuses 0x420 and + * 0x430). + */ + imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - eth_mac1: mac-address@90 { + eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; - eth_mac2: mac-address@96 { + eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 2b6d3f4ff5d93..8a2ec90b493d9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -593,15 +593,28 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mq_uid: soc-uid@4 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; };