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Tue, 20 Dec 2022 08:05:25 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 20 Dec 2022 08:05:25 -0800 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Tue, 20 Dec 2022 08:05:21 -0800 From: Sumit Gupta To: , , , , , , , , , , CC: , , , , Subject: [Patch v1 10/10] memory: tegra: make cluster bw request a multiple of mc_channels Date: Tue, 20 Dec 2022 21:32:40 +0530 Message-ID: <20221220160240.27494-11-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221220160240.27494-1-sumitg@nvidia.com> References: <20221220160240.27494-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT106:EE_|MN2PR12MB4487:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ccb5cd1-3ef7-4100-85dc-08dae2a40b23 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2022 16:05:41.3706 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ccb5cd1-3ef7-4100-85dc-08dae2a40b23 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT106.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4487 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org CPU opp table have bandwidth data per MC channel. The actual bandwidth depends on number of MC channels which can change as per the boot config for a board. So, multiply the bandwidth request for CPU clusters with number of enabled MC channels. This is not required to be done for other MC clients. Signed-off-by: Sumit Gupta --- drivers/memory/tegra/tegra234.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 82ce6c3c3eb0..a45fc99b9c82 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -834,6 +834,29 @@ static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst) return 0; } +static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + struct tegra_icc_node *tnode = NULL; + struct tegra_mc *mc = NULL; + + if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 || + node->id == TEGRA_ICC_MC_CPU_CLUSTER1 || + node->id == TEGRA_ICC_MC_CPU_CLUSTER2) { + if (node->data) { + tnode = node->data; + mc = tnode->mc; + if (mc) + peak_bw = peak_bw * mc->num_channels; + } + } + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + static struct icc_node* tegra234_mc_of_icc_xlate(struct of_phandle_args *spec, void *data) { @@ -866,7 +889,7 @@ static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *pea static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = { .xlate = tegra234_mc_of_icc_xlate, .get_bw = tegra234_mc_icc_get_init_bw, - .aggregate = icc_std_aggregate, + .aggregate = tegra234_mc_icc_aggregate, .set = tegra234_mc_icc_set, };