| Message ID | 20230417063942.3141-4-mason.huo@starfivetech.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | viresh kumar |
| Headers | show |
| Series | Add JH7110 cpufreq support | expand |
Hey Mason, Just one minor comment in passing.. On Mon, Apr 17, 2023 at 02:39:42PM +0800, Mason Huo wrote: > Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. > It supports up to 4 cpu frequency loads. > > Signed-off-by: Mason Huo <mason.huo@starfivetech.com> > --- > .../jh7110-starfive-visionfive-2.dtsi | 17 ++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++ > 2 files changed, 50 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index cca1c8040801..b25e6d68ce53 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -227,3 +227,20 @@ &uart0 { > pinctrl-0 = <&uart0_pins>; > status = "okay"; > }; > + > +&U74_1 { > + cpu-supply = <&vdd_cpu>; > +}; > + > +&U74_2 { > + cpu-supply = <&vdd_cpu>; > +}; > + > +&U74_3 { > + cpu-supply = <&vdd_cpu>; > +}; > + > +&U74_4 { > + cpu-supply = <&vdd_cpu>; > +}; > + Applying: riscv: dts: starfive: Add cpu scaling for JH7110 SoC /stuff/linux/.git/rebase-apply/patch:30: new blank line at EOF. + warning: 1 line adds whitespace errors. Cheers, Conor.
On 2023/4/19 1:28, Conor Dooley wrote: > Hey Mason, > > Just one minor comment in passing.. > > On Mon, Apr 17, 2023 at 02:39:42PM +0800, Mason Huo wrote: >> Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. >> It supports up to 4 cpu frequency loads. >> >> Signed-off-by: Mason Huo <mason.huo@starfivetech.com> >> --- >> .../jh7110-starfive-visionfive-2.dtsi | 17 ++++++++++ >> arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++ >> 2 files changed, 50 insertions(+) >> >> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> index cca1c8040801..b25e6d68ce53 100644 >> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi >> @@ -227,3 +227,20 @@ &uart0 { >> pinctrl-0 = <&uart0_pins>; >> status = "okay"; >> }; >> + >> +&U74_1 { >> + cpu-supply = <&vdd_cpu>; >> +}; >> + >> +&U74_2 { >> + cpu-supply = <&vdd_cpu>; >> +}; >> + >> +&U74_3 { >> + cpu-supply = <&vdd_cpu>; >> +}; >> + >> +&U74_4 { >> + cpu-supply = <&vdd_cpu>; >> +}; >> + > > Applying: riscv: dts: starfive: Add cpu scaling for JH7110 SoC > /stuff/linux/.git/rebase-apply/patch:30: new blank line at EOF. > + > warning: 1 line adds whitespace errors. > > Cheers, > Conor. > Hi Conor, Will fix it soon. Thanks Mason
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index cca1c8040801..b25e6d68ce53 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -227,3 +227,20 @@ &uart0 { pinctrl-0 = <&uart0_pins>; status = "okay"; }; + +&U74_1 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_2 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_3 { + cpu-supply = <&vdd_cpu>; +}; + +&U74_4 { + cpu-supply = <&vdd_cpu>; +}; + diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4c5fdb905da8..7eef88d2cedb 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -53,6 +53,9 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -79,6 +82,9 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -105,6 +111,9 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -131,6 +140,9 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -164,6 +176,27 @@ core4 { }; }; + cpu_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <800000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-microvolt = <800000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1040000>; + }; + }; + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin";
Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. It supports up to 4 cpu frequency loads. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> --- .../jh7110-starfive-visionfive-2.dtsi | 17 ++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++ 2 files changed, 50 insertions(+)